Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24443727	6563	0	0
EscTimeoutStoppedByClReset_A	24443117	3494029	0	0
EscTimeoutTriggersReset_A	4939326	337	0	0
RomAllowActiveState_A	24443117	60660	0	0
RomAllowCheckGoodState_A	24443117	60711	0	0
RomBlockActiveState_A	24443117	27681	0	0
RomBlockCheckGoodState_A	24443117	431164	0	0
RomIntgChkDisFalse_A	24443117	23676234	0	0
RomIntgChkDisTrue_A	24443117	238647	0	0
RstreqChkEsctimeout_A	24443117	4359	0	0
RstreqChkFsmterm_A	24443117	140	0	0
RstreqChkGlbesc_A	24443117	4359	0	0
RstreqChkMainpd_A	24443117	1052937	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443727	6563	0	0
T8	738	7	0	0
T9	9452	0	0	0
T10	2650	0	0	0
T11	0	270	0	0
T13	1708	0	0	0
T14	865	0	0	0
T21	9949	0	0	0
T36	18702	0	0	0
T39	1407	0	0	0
T40	0	175	0	0
T41	0	19	0	0
T42	4631	0	0	0
T43	9794	0	0	0
T161	0	23	0	0
T162	0	38	0	0
T163	0	33	0	0
T164	0	13	0	0
T165	0	32	0	0
T166	0	55	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	3494029	0	0
T1	6833	39	0	0
T2	3695	38	0	0
T3	1415	26	0	0
T4	2259	0	0	0
T5	27090	5683	0	0
T6	1295	13	0	0
T7	15583	1805	0	0
T8	737	21	0	0
T9	9452	540	0	0
T10	2650	58	0	0
T21	0	1242	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4939326	337	0	0
T8	290	5	0	0
T9	6158	0	0	0
T10	266	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T13	522	0	0	0
T14	591	0	0	0
T21	971	0	0	0
T36	6018	0	0	0
T39	1721	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	361	0	0	0
T43	1070	0	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	3	0	0
T167	0	4	0	0
T168	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	60660	0	0
T1	6833	5	0	0
T2	3695	6	0	0
T3	1415	3	0	0
T4	2259	5	0	0
T5	27090	84	0	0
T6	1295	10	0	0
T7	15583	84	0	0
T8	737	3	0	0
T9	9452	43	0	0
T10	2650	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	60711	0	0
T1	6833	5	0	0
T2	3695	6	0	0
T3	1415	3	0	0
T4	2259	5	0	0
T5	27090	84	0	0
T6	1295	10	0	0
T7	15583	84	0	0
T8	737	3	0	0
T9	9452	43	0	0
T10	2650	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	27681	0	0
T11	15868	0	0	0
T13	1707	222	0	0
T14	865	79	0	0
T15	1068	0	0	0
T17	866	0	0	0
T36	18701	0	0	0
T39	1406	0	0	0
T42	4631	0	0	0
T43	9794	0	0	0
T45	0	551	0	0
T47	1549	0	0	0
T169	0	15	0	0
T170	0	3	0	0
T171	0	773	0	0
T172	0	809	0	0
T173	0	6	0	0
T174	0	181	0	0
T175	0	358	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	431164	0	0
T5	27090	2148	0	0
T6	1295	0	0	0
T7	15583	731	0	0
T8	737	0	0	0
T9	9452	92	0	0
T10	2650	0	0	0
T13	1707	70	0	0
T14	865	0	0	0
T21	9949	0	0	0
T22	0	2754	0	0
T23	0	3626	0	0
T24	0	5578	0	0
T36	0	1506	0	0
T37	0	2240	0	0
T39	1406	0	0	0
T87	0	575	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	23676234	0	0
T1	6833	6757	0	0
T2	3695	3206	0	0
T3	1415	1329	0	0
T4	2259	2187	0	0
T5	27090	26117	0	0
T6	1295	1237	0	0
T7	15583	15490	0	0
T8	737	586	0	0
T9	9452	9094	0	0
T10	2650	2372	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	238647	0	0
T5	27090	807	0	0
T6	1295	0	0	0
T7	15583	0	0	0
T8	737	0	0	0
T9	9452	0	0	0
T10	2650	0	0	0
T13	1707	35	0	0
T14	865	64	0	0
T21	9949	0	0	0
T36	0	616	0	0
T39	1406	0	0	0
T45	0	1246	0	0
T170	0	367	0	0
T171	0	2255	0	0
T172	0	1789	0	0
T176	0	1003	0	0
T177	0	419	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	4359	0	0
T8	737	1	0	0
T9	9452	0	0	0
T10	2650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1707	4	0	0
T14	865	2	0	0
T15	0	2	0	0
T21	9949	0	0	0
T22	0	75	0	0
T23	0	80	0	0
T36	18701	0	0	0
T38	0	7	0	0
T39	1406	0	0	0
T42	4631	0	0	0
T43	9794	0	0	0
T48	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	140	0	0
T18	15398	20	0	0
T19	0	40	0	0
T20	0	40	0	0
T25	0	20	0	0
T26	0	20	0	0
T27	4195	0	0	0
T28	7932	0	0	0
T29	2340	0	0	0
T30	3043	0	0	0
T31	1520	0	0	0
T32	1859	0	0	0
T33	3509	0	0	0
T34	1994	0	0	0
T35	17870	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	4359	0	0
T8	737	1	0	0
T9	9452	0	0	0
T10	2650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1707	4	0	0
T14	865	2	0	0
T15	0	2	0	0
T21	9949	0	0	0
T22	0	75	0	0
T23	0	80	0	0
T36	18701	0	0	0
T38	0	7	0	0
T39	1406	0	0	0
T42	4631	0	0	0
T43	9794	0	0	0
T48	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	1052937	0	0
T2	3695	22	0	0
T3	1415	0	0	0
T4	2259	0	0	0
T5	27090	3345	0	0
T6	1295	0	0	0
T7	15583	1081	0	0
T8	737	0	0	0
T9	9452	173	0	0
T10	2650	17	0	0
T13	0	72	0	0
T14	0	15	0	0
T17	0	5	0	0
T21	9949	0	0	0
T22	0	18942	0	0
T36	0	1874	0	0