Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

195618

1

T1

89

T2

58

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	368090	1			T1	169		T2	88		T3	15
values[0x0]	169319	1			T1	85		T2	16		T3	6
values[0x1]	170417	1			T1	88		T2	17		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

302512

1

T1

136

T2

73

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3114	1			T4	1		T7	4		T89	6
valid_sources[0x01]	2057	1			T7	6		T24	6		T13	3
valid_sources[0x02]	4034	1			T4	2		T7	2		T24	9
valid_sources[0x03]	4211	1			T2	2		T4	1		T7	3
valid_sources[0x04]	2058	1			T3	3		T4	4		T7	4
valid_sources[0x05]	2191	1			T7	4		T89	2		T24	13
valid_sources[0x06]	2296	1			T2	4		T3	1		T10	50
valid_sources[0x07]	2153	1			T7	3		T25	1		T24	3
valid_sources[0x08]	3893	1			T4	1		T7	4		T89	3
valid_sources[0x09]	2747	1			T4	2		T7	3		T10	5
valid_sources[0x0a]	8300	1			T4	1		T7	2		T24	5
valid_sources[0x0b]	2250	1			T2	1		T4	1		T7	2
valid_sources[0x0c]	2138	1			T24	3		T13	5		T38	1
valid_sources[0x0d]	2199	1			T4	1		T7	4		T24	1
valid_sources[0x0e]	2426	1			T4	1		T7	2		T24	7
valid_sources[0x0f]	2315	1			T3	3		T4	2		T7	1
valid_sources[0x10]	1926	1			T7	5		T89	6		T24	6
valid_sources[0x11]	1891	1			T2	1		T4	2		T7	4
valid_sources[0x12]	3289	1			T2	2		T7	3		T89	4
valid_sources[0x13]	2105	1			T2	3		T4	1		T7	1
valid_sources[0x14]	2645	1			T4	1		T7	1		T89	4
valid_sources[0x15]	2122	1			T7	3		T10	2		T24	7
valid_sources[0x16]	2443	1			T7	4		T24	2		T37	1
valid_sources[0x17]	2102	1			T4	2		T7	2		T37	1
valid_sources[0x18]	2253	1			T4	2		T7	3		T24	5
valid_sources[0x19]	3128	1			T7	6		T89	4		T24	3
valid_sources[0x1a]	2449	1			T7	2		T37	3		T13	16
valid_sources[0x1b]	2083	1			T4	2		T7	3		T24	3
valid_sources[0x1c]	2513	1			T4	3		T7	1		T10	6
valid_sources[0x1d]	3909	1			T4	1		T7	2		T24	3
valid_sources[0x1e]	2891	1			T4	3		T7	3		T24	13
valid_sources[0x1f]	2696	1			T4	1		T7	6		T37	1
valid_sources[0x20]	2263	1			T4	1		T6	27		T7	3
valid_sources[0x21]	2108	1			T4	1		T7	5		T25	1
valid_sources[0x22]	2331	1			T4	1		T7	6		T24	5
valid_sources[0x23]	2044	1			T4	1		T7	8		T89	1
valid_sources[0x24]	2669	1			T4	2		T7	5		T24	1
valid_sources[0x25]	2410	1			T4	6		T7	4		T24	3
valid_sources[0x26]	3394	1			T7	7		T24	1		T37	2
valid_sources[0x27]	2459	1			T7	7		T24	5		T37	2
valid_sources[0x28]	2408	1			T4	1		T7	3		T24	2
valid_sources[0x29]	4985	1			T2	3		T4	2		T7	6
valid_sources[0x2a]	2500	1			T4	1		T7	1		T24	1
valid_sources[0x2b]	1994	1			T2	2		T4	1		T7	3
valid_sources[0x2c]	3774	1			T3	4		T4	1		T7	6
valid_sources[0x2d]	1888	1			T7	5		T24	2		T37	2
valid_sources[0x2e]	2278	1			T4	1		T7	8		T10	1
valid_sources[0x2f]	2037	1			T7	1		T37	4		T13	10
valid_sources[0x30]	4547	1			T7	1		T37	1		T13	9
valid_sources[0x31]	2362	1			T2	1		T7	4		T25	1
valid_sources[0x32]	2074	1			T7	3		T89	5		T37	1
valid_sources[0x33]	2009	1			T7	4		T24	3		T13	27
valid_sources[0x34]	3990	1			T4	1		T7	3		T24	3
valid_sources[0x35]	2665	1			T4	7		T7	6		T89	5
valid_sources[0x36]	2628	1			T7	4		T89	11		T24	1
valid_sources[0x37]	2530	1			T4	1		T7	6		T24	4
valid_sources[0x38]	1991	1			T4	2		T7	1		T13	4
valid_sources[0x39]	3907	1			T4	2		T7	4		T25	2
valid_sources[0x3a]	2104	1			T7	2		T25	1		T24	3
valid_sources[0x3b]	2401	1			T7	4		T89	3		T13	11
valid_sources[0x3c]	2055	1			T4	1		T7	6		T37	1
valid_sources[0x3d]	3794	1			T7	2		T24	3		T37	1
valid_sources[0x3e]	3536	1			T4	1		T7	3		T25	1
valid_sources[0x3f]	2947	1			T4	1		T5	21		T7	1
valid_sources[0x40]	2179	1			T4	1		T7	2		T24	3
valid_sources[0x41]	3732	1			T7	3		T25	1		T37	1
valid_sources[0x42]	2077	1			T4	1		T7	2		T89	9
valid_sources[0x43]	2204	1			T4	1		T7	6		T89	4
valid_sources[0x44]	2330	1			T1	342		T7	2		T89	6
valid_sources[0x45]	3081	1			T4	3		T7	6		T24	4
valid_sources[0x46]	3017	1			T7	6		T25	1		T24	3
valid_sources[0x47]	1941	1			T2	1		T7	4		T37	1
valid_sources[0x48]	2305	1			T7	4		T24	4		T13	3
valid_sources[0x49]	2220	1			T4	1		T7	3		T25	1
valid_sources[0x4a]	2233	1			T4	1		T7	6		T24	4
valid_sources[0x4b]	2083	1			T4	2		T7	2		T24	7
valid_sources[0x4c]	1987	1			T2	3		T4	1		T7	3
valid_sources[0x4d]	2280	1			T4	1		T7	2		T25	2
valid_sources[0x4e]	2212	1			T4	1		T7	4		T8	1
valid_sources[0x4f]	3724	1			T7	3		T24	4		T37	1
valid_sources[0x50]	3515	1			T2	8		T4	2		T7	2
valid_sources[0x51]	2264	1			T7	2		T24	8		T37	1
valid_sources[0x52]	2814	1			T4	2		T7	3		T13	7
valid_sources[0x53]	2555	1			T7	3		T24	1		T13	3
valid_sources[0x54]	3205	1			T4	1		T7	2		T89	3
valid_sources[0x55]	2560	1			T7	2		T89	4		T37	1
valid_sources[0x56]	4764	1			T7	5		T13	16		T14	31
valid_sources[0x57]	2104	1			T7	8		T89	4		T24	3
valid_sources[0x58]	1939	1			T3	3		T4	2		T7	1
valid_sources[0x59]	3501	1			T2	2		T7	3		T24	8
valid_sources[0x5a]	3371	1			T4	3		T7	4		T25	1
valid_sources[0x5b]	3341	1			T7	4		T24	1		T13	3
valid_sources[0x5c]	2208	1			T4	1		T7	3		T24	18
valid_sources[0x5d]	2352	1			T25	1		T24	5		T37	1
valid_sources[0x5e]	2177	1			T4	1		T7	7		T24	1
valid_sources[0x5f]	2531	1			T4	1		T7	4		T13	14
valid_sources[0x60]	3325	1			T2	2		T7	4		T37	3
valid_sources[0x61]	1897	1			T4	1		T7	3		T24	4
valid_sources[0x62]	1841	1			T4	2		T7	12		T24	8
valid_sources[0x63]	2054	1			T4	1		T7	5		T25	1
valid_sources[0x64]	4598	1			T7	2		T24	2		T37	1
valid_sources[0x65]	2036	1			T4	1		T7	1		T24	1
valid_sources[0x66]	3625	1			T7	2		T89	3		T37	2
valid_sources[0x67]	4715	1			T2	2		T7	1		T25	1
valid_sources[0x68]	2071	1			T7	1		T24	4		T37	3
valid_sources[0x69]	2002	1			T2	11		T4	2		T7	2
valid_sources[0x6a]	2208	1			T4	1		T7	2		T24	3
valid_sources[0x6b]	2059	1			T2	6		T7	1		T24	2
valid_sources[0x6c]	1923	1			T3	3		T4	3		T7	2
valid_sources[0x6d]	2346	1			T7	3		T24	11		T37	1
valid_sources[0x6e]	5865	1			T4	1		T7	7		T25	1
valid_sources[0x6f]	1986	1			T2	1		T7	6		T25	1
valid_sources[0x70]	1940	1			T2	2		T7	4		T13	7
valid_sources[0x71]	2979	1			T4	1		T7	2		T24	7
valid_sources[0x72]	2881	1			T4	1		T7	1		T24	4
valid_sources[0x73]	2101	1			T4	3		T7	4		T24	3
valid_sources[0x74]	2944	1			T4	1		T7	8		T24	4
valid_sources[0x75]	2024	1			T3	2		T7	6		T37	2
valid_sources[0x76]	2003	1			T4	1		T7	4		T89	3
valid_sources[0x77]	2321	1			T7	3		T25	1		T24	2
valid_sources[0x78]	1895	1			T4	2		T7	1		T25	1
valid_sources[0x79]	3076	1			T4	1		T7	5		T89	8
valid_sources[0x7a]	2546	1			T4	3		T7	3		T24	3
valid_sources[0x7b]	5022	1			T4	2		T7	4		T24	3
valid_sources[0x7c]	1910	1			T7	6		T24	9		T13	17
valid_sources[0x7d]	2475	1			T7	3		T24	3		T13	10
valid_sources[0x7e]	1973	1			T2	6		T4	1		T7	5
valid_sources[0x7f]	3041	1			T2	2		T7	2		T24	1
valid_sources[0x80]	3594	1			T7	4		T10	1		T24	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97906

1

T1

36

T2

51

T3

6

values[0x0]

all_enables

biggest_size

63154

1

T1

38

T2

6

T3

2

values[0x1]

all_enables

biggest_size

34558

1

T1

15

T2

1

T3

1