SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35168 | 1 | T7 | 304 | T9 | 396 | T24 | 269 | ||||
others[1] | 34749 | 1 | T7 | 299 | T9 | 418 | T10 | 1 | ||||
others[2] | 35067 | 1 | T7 | 275 | T9 | 388 | T10 | 1 | ||||
others[3] | 58505 | 1 | T7 | 525 | T9 | 652 | T24 | 503 | ||||
false | 19382 | 1 | T1 | 38 | T7 | 50 | T9 | 50 | ||||
true | 29394 | 1 | T1 | 40 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35091 | 1 | T7 | 302 | T9 | 402 | T24 | 304 | ||||
others[1] | 34916 | 1 | T7 | 332 | T9 | 414 | T24 | 296 | ||||
others[2] | 34807 | 1 | T7 | 295 | T9 | 402 | T24 | 315 | ||||
others[3] | 58535 | 1 | T7 | 471 | T9 | 667 | T10 | 1 | ||||
false | 12304 | 1 | T1 | 19 | T7 | 50 | T9 | 50 | ||||
true | 22360 | 1 | T1 | 21 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 662 | 1 | T89 | 7 | T13 | 2 | T21 | 8 | ||||
others[1] | 628 | 1 | T10 | 1 | T89 | 8 | T13 | 1 | ||||
others[2] | 704 | 1 | T89 | 4 | T13 | 1 | T21 | 5 | ||||
others[3] | 1152 | 1 | T2 | 1 | T25 | 3 | T89 | 7 | ||||
false | 13442 | 1 | T1 | 2 | T2 | 21 | T3 | 1 | ||||
true | 3883 | 1 | T2 | 7 | T10 | 2 | T25 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |