Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24376340	16295	0	0
intr_enable_rd_A	24376340	37826	0	0
reset_en_rd_A	24376340	1403	0	0
reset_en_regwen_rd_A	24376340	1207	0	0
wake_info_capture_dis_rd_A	24376340	1042	0	0
wakeup_en_rd_A	24376340	2954	0	0
wakeup_en_regwen_rd_A	24376340	1180	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	16295	0	0
T14	263813	12	0	0
T22	0	14	0	0
T23	0	167	0	0
T39	4130	0	0	0
T43	1914	0	0	0
T52	0	44	0	0
T54	7505	0	0	0
T55	7985	0	0	0
T132	0	14	0	0
T133	0	16	0	0
T134	0	16	0	0
T135	0	61	0	0
T136	0	3	0	0
T137	0	14	0	0
T138	1526	0	0	0
T139	2376	0	0	0
T140	2270	0	0	0
T141	1701	0	0	0
T142	4145	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	37826	0	0
T6	1582	5	0	0
T7	30447	0	0	0
T8	1743	0	0	0
T9	20095	0	0	0
T10	6082	0	0	0
T13	51164	0	0	0
T22	0	2000	0	0
T24	49068	0	0	0
T25	3707	0	0	0
T37	13052	0	0	0
T38	0	8	0	0
T48	0	173	0	0
T54	0	11	0	0
T89	4390	0	0	0
T94	0	2	0	0
T95	0	68	0	0
T96	0	12	0	0
T98	0	105	0	0
T142	0	106	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	1403	0	0
T22	435655	7	0	0
T23	429208	0	0	0
T40	10732	0	0	0
T41	2683	0	0	0
T42	1208	0	0	0
T48	23433	0	0	0
T49	0	31	0	0
T76	0	18	0	0
T81	0	2	0	0
T90	0	6	0	0
T93	5037	0	0	0
T94	1508	0	0	0
T95	4791	0	0	0
T96	3415	0	0	0
T132	0	3	0	0
T143	0	11	0	0
T144	0	8	0	0
T145	0	4	0	0
T146	0	14	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	1207	0	0
T22	435655	8	0	0
T23	429208	0	0	0
T40	10732	0	0	0
T41	2683	0	0	0
T42	1208	0	0	0
T48	23433	0	0	0
T49	0	34	0	0
T81	0	9	0	0
T90	0	7	0	0
T93	5037	0	0	0
T94	1508	0	0	0
T95	4791	0	0	0
T96	3415	0	0	0
T132	0	4	0	0
T143	0	16	0	0
T144	0	9	0	0
T145	0	9	0	0
T147	0	3	0	0
T148	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	1042	0	0
T22	435655	1	0	0
T23	429208	0	0	0
T40	10732	0	0	0
T41	2683	0	0	0
T42	1208	0	0	0
T48	23433	0	0	0
T72	0	3	0	0
T76	0	5	0	0
T81	0	14	0	0
T93	5037	0	0	0
T94	1508	0	0	0
T95	4791	0	0	0
T96	3415	0	0	0
T132	0	1	0	0
T143	0	10	0	0
T144	0	5	0	0
T145	0	4	0	0
T147	0	3	0	0
T148	0	9	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	2954	0	0
T22	435655	14	0	0
T23	429208	0	0	0
T40	10732	0	0	0
T41	2683	0	0	0
T42	1208	0	0	0
T48	23433	0	0	0
T76	0	17	0	0
T81	0	12	0	0
T90	0	10	0	0
T93	5037	0	0	0
T94	1508	0	0	0
T95	4791	0	0	0
T96	3415	0	0	0
T132	0	5	0	0
T143	0	3	0	0
T144	0	6	0	0
T145	0	3	0	0
T147	0	3	0	0
T148	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24376340	1180	0	0
T12	844	0	0	0
T47	2836	0	0	0
T49	0	4	0	0
T52	450080	0	0	0
T76	0	13	0	0
T81	0	15	0	0
T90	0	12	0	0
T126	42815	0	0	0
T127	2516	0	0	0
T128	131658	0	0	0
T132	297991	16	0	0
T143	0	10	0	0
T144	0	2	0	0
T145	0	8	0	0
T146	0	6	0	0
T148	0	7	0	0
T149	15440	0	0	0
T150	58347	0	0	0
T151	8241	0	0	0