Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71429217	145575	0	0
StatusRise_A	71429217	162395	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71429217	145575	0	0
T1	33519	100	0	0
T2	24678	54	0	0
T3	3960	6	0	0
T4	7122	27	0	0
T5	5148	12	0	0
T6	4746	6	0	0
T7	91341	216	0	0
T8	5229	3	0	0
T9	60285	207	0	0
T10	18246	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71429217	162395	0	0
T1	33519	106	0	0
T2	24678	60	0	0
T3	3960	9	0	0
T4	7122	29	0	0
T5	5148	15	0	0
T6	4746	9	0	0
T7	91341	219	0	0
T8	5229	9	0	0
T9	60285	209	0	0
T10	18246	24	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23809739	54053	0	0
StatusRise_A	23809739	60155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	54053	0	0
T1	11173	36	0	0
T2	8226	18	0	0
T3	1320	2	0	0
T4	2374	9	0	0
T5	1716	4	0	0
T6	1582	2	0	0
T7	30447	89	0	0
T8	1743	1	0	0
T9	20095	87	0	0
T10	6082	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	60155	0	0
T1	11173	38	0	0
T2	8226	20	0	0
T3	1320	3	0	0
T4	2374	10	0	0
T5	1716	5	0	0
T6	1582	3	0	0
T7	30447	90	0	0
T8	1743	3	0	0
T9	20095	88	0	0
T10	6082	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23809739	54053	0	0
StatusRise_A	23809739	60155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	54053	0	0
T1	11173	36	0	0
T2	8226	18	0	0
T3	1320	2	0	0
T4	2374	9	0	0
T5	1716	4	0	0
T6	1582	2	0	0
T7	30447	89	0	0
T8	1743	1	0	0
T9	20095	87	0	0
T10	6082	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	60155	0	0
T1	11173	38	0	0
T2	8226	20	0	0
T3	1320	3	0	0
T4	2374	10	0	0
T5	1716	5	0	0
T6	1582	3	0	0
T7	30447	90	0	0
T8	1743	3	0	0
T9	20095	88	0	0
T10	6082	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23809739	37469	0	0
StatusRise_A	23809739	42085	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	37469	0	0
T1	11173	28	0	0
T2	8226	18	0	0
T3	1320	2	0	0
T4	2374	9	0	0
T5	1716	4	0	0
T6	1582	2	0	0
T7	30447	38	0	0
T8	1743	1	0	0
T9	20095	33	0	0
T10	6082	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	42085	0	0
T1	11173	30	0	0
T2	8226	20	0	0
T3	1320	3	0	0
T4	2374	9	0	0
T5	1716	5	0	0
T6	1582	3	0	0
T7	30447	39	0	0
T8	1743	3	0	0
T9	20095	33	0	0
T10	6082	8	0	0