Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23810318	5809	0	0
EscTimeoutStoppedByClReset_A	23809739	3288432	0	0
EscTimeoutTriggersReset_A	5016616	321	0	0
RomAllowActiveState_A	23809739	59753	0	0
RomAllowCheckGoodState_A	23809739	59803	0	0
RomBlockActiveState_A	23809739	26593	0	0
RomBlockCheckGoodState_A	23809739	434665	0	0
RomIntgChkDisFalse_A	23809739	23142042	0	0
RomIntgChkDisTrue_A	23809739	145139	0	0
RstreqChkEsctimeout_A	23809739	4164	0	0
RstreqChkFsmterm_A	23809739	120	0	0
RstreqChkGlbesc_A	23809739	4164	0	0
RstreqChkMainpd_A	23809739	959632	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23810318	5809	0	0
T11	1266	10	0	0
T12	0	8	0	0
T22	435656	0	0	0
T40	10733	0	0	0
T41	2684	0	0	0
T48	23434	0	0	0
T68	3982	0	0	0
T88	10344	0	0	0
T93	5038	0	0	0
T103	51448	0	0	0
T149	0	254	0	0
T152	0	28	0	0
T153	0	56	0	0
T154	0	14	0	0
T155	0	35	0	0
T156	0	96	0	0
T157	0	271	0	0
T158	0	5	0	0
T159	2311	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	3288432	0	0
T1	11173	2456	0	0
T2	8226	362	0	0
T3	1320	15	0	0
T4	2374	32	0	0
T5	1716	45	0	0
T6	1582	12	0	0
T7	30447	5483	0	0
T8	1743	11	0	0
T9	20095	2486	0	0
T10	6082	233	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5016616	321	0	0
T8	212	3	0	0
T9	9300	0	0	0
T10	460	0	0	0
T11	0	3	0	0
T12	0	4	0	0
T13	11217	0	0	0
T21	362	0	0	0
T24	5785	0	0	0
T25	290	0	0	0
T37	1545	0	0	0
T38	1010	0	0	0
T89	657	0	0	0
T149	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	2	0	0
T160	0	7	0	0
T161	0	3	0	0
T162	0	6	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	59753	0	0
T1	11173	38	0	0
T2	8226	13	0	0
T3	1320	3	0	0
T4	2374	10	0	0
T5	1716	5	0	0
T6	1582	3	0	0
T7	30447	90	0	0
T8	1743	3	0	0
T9	20095	88	0	0
T10	6082	8	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	59803	0	0
T1	11173	38	0	0
T2	8226	14	0	0
T3	1320	3	0	0
T4	2374	10	0	0
T5	1716	5	0	0
T6	1582	3	0	0
T7	30447	90	0	0
T8	1743	3	0	0
T9	20095	88	0	0
T10	6082	8	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	26593	0	0
T9	20095	8	0	0
T10	6082	1536	0	0
T13	51164	0	0	0
T14	263813	0	0	0
T21	4772	0	0	0
T24	49068	0	0	0
T25	3707	0	0	0
T37	13052	0	0	0
T38	3159	0	0	0
T48	0	11	0	0
T89	4390	0	0	0
T96	0	618	0	0
T163	0	466	0	0
T164	0	119	0	0
T165	0	25	0	0
T166	0	781	0	0
T167	0	1142	0	0
T168	0	1162	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	434665	0	0
T1	11173	436	0	0
T2	8226	0	0	0
T3	1320	0	0	0
T4	2374	0	0	0
T5	1716	0	0	0
T6	1582	0	0	0
T7	30447	2298	0	0
T8	1743	0	0	0
T9	20095	1086	0	0
T10	6082	1053	0	0
T13	0	779	0	0
T14	0	3386	0	0
T24	0	3740	0	0
T37	0	299	0	0
T38	0	115	0	0
T54	0	344	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	23142042	0	0
T1	11173	11014	0	0
T2	8226	7271	0	0
T3	1320	1232	0	0
T4	2374	2308	0	0
T5	1716	1298	0	0
T6	1582	1519	0	0
T7	30447	28391	0	0
T8	1743	1580	0	0
T9	20095	20014	0	0
T10	6082	3986	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	145139	0	0
T7	30447	1974	0	0
T8	1743	0	0	0
T9	20095	0	0	0
T10	6082	1941	0	0
T13	51164	0	0	0
T21	4772	0	0	0
T24	49068	930	0	0
T25	3707	0	0	0
T37	13052	0	0	0
T89	4390	0	0	0
T96	0	1352	0	0
T163	0	1372	0	0
T164	0	171	0	0
T166	0	1199	0	0
T167	0	140	0	0
T168	0	225	0	0
T169	0	1185	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	4164	0	0
T2	8226	7	0	0
T3	1320	0	0	0
T4	2374	0	0	0
T5	1716	0	0	0
T6	1582	0	0	0
T7	30447	0	0	0
T8	1743	1	0	0
T9	20095	0	0	0
T10	6082	2	0	0
T11	0	1	0	0
T13	0	14	0	0
T14	0	53	0	0
T22	0	86	0	0
T25	3707	0	0	0
T39	0	6	0	0
T40	0	6	0	0
T43	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	120	0	0
T18	8092	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T28	1191	0	0	0
T29	1584	0	0	0
T30	4603	0	0	0
T31	3899	0	0	0
T32	6459	0	0	0
T33	6911	0	0	0
T34	1332	0	0	0
T35	17913	0	0	0
T36	72503	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	4164	0	0
T2	8226	7	0	0
T3	1320	0	0	0
T4	2374	0	0	0
T5	1716	0	0	0
T6	1582	0	0	0
T7	30447	0	0	0
T8	1743	1	0	0
T9	20095	0	0	0
T10	6082	2	0	0
T11	0	1	0	0
T13	0	14	0	0
T14	0	53	0	0
T22	0	86	0	0
T25	3707	0	0	0
T39	0	6	0	0
T40	0	6	0	0
T43	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23809739	959632	0	0
T1	11173	1342	0	0
T2	8226	222	0	0
T3	1320	0	0	0
T4	2374	0	0	0
T5	1716	0	0	0
T6	1582	0	0	0
T7	30447	3725	0	0
T8	1743	0	0	0
T9	20095	1540	0	0
T10	6082	722	0	0
T13	0	2063	0	0
T24	0	3662	0	0
T25	0	343	0	0
T37	0	658	0	0
T38	0	132	0	0