Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	529301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208104

1

T2

742

T3

1

T5

203

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	391803	1			T1	1		T2	1440		T3	1
values[0x0]	172263	1			T2	719		T5	225		T6	220
values[0x1]	173339	1			T2	695		T5	227		T6	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	418854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

318551

1

T2

1162

T3

1

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2322	1			T2	19		T5	9		T9	4
valid_sources[0x01]	2385	1			T2	18		T6	10		T7	13
valid_sources[0x02]	2665	1			T2	7		T5	4		T7	12
valid_sources[0x03]	3133	1			T2	12		T6	2		T7	12
valid_sources[0x04]	3949	1			T2	9		T5	4		T6	14
valid_sources[0x05]	2410	1			T2	11		T6	4		T7	12
valid_sources[0x06]	2400	1			T2	7		T5	2		T8	3
valid_sources[0x07]	2609	1			T2	13		T5	6		T6	5
valid_sources[0x08]	2386	1			T2	10		T5	3		T6	5
valid_sources[0x09]	2829	1			T2	6		T5	5		T7	12
valid_sources[0x0a]	2627	1			T2	8		T6	5		T7	24
valid_sources[0x0b]	2245	1			T2	8		T5	2		T6	8
valid_sources[0x0c]	2290	1			T2	9		T5	5		T6	6
valid_sources[0x0d]	3584	1			T2	13		T5	5		T6	15
valid_sources[0x0e]	3948	1			T2	14		T9	6		T13	44
valid_sources[0x0f]	2527	1			T2	3		T5	3		T9	10
valid_sources[0x10]	2351	1			T2	4		T6	5		T8	3
valid_sources[0x11]	3122	1			T2	14		T6	6		T7	13
valid_sources[0x12]	2362	1			T2	7		T5	3		T6	5
valid_sources[0x13]	2521	1			T2	20		T6	2		T9	9
valid_sources[0x14]	3289	1			T2	15		T6	10		T7	11
valid_sources[0x15]	2484	1			T2	29		T5	7		T6	1
valid_sources[0x16]	3432	1			T2	14		T5	2		T6	2
valid_sources[0x17]	2344	1			T2	16		T5	4		T6	19
valid_sources[0x18]	3590	1			T2	11		T6	3		T7	23
valid_sources[0x19]	3080	1			T2	11		T5	1		T7	11
valid_sources[0x1a]	2389	1			T2	5		T5	2		T7	24
valid_sources[0x1b]	2191	1			T2	17		T8	1		T9	3
valid_sources[0x1c]	3073	1			T2	8		T5	3		T7	12
valid_sources[0x1d]	3438	1			T2	19		T5	1		T8	6
valid_sources[0x1e]	4521	1			T2	15		T5	2		T13	116
valid_sources[0x1f]	2535	1			T2	15		T5	9		T7	12
valid_sources[0x20]	2896	1			T2	5		T5	1		T6	1
valid_sources[0x21]	2605	1			T2	18		T9	6		T13	56
valid_sources[0x22]	2205	1			T2	9		T5	5		T6	5
valid_sources[0x23]	2636	1			T2	15		T5	6		T6	4
valid_sources[0x24]	2509	1			T2	8		T5	1		T6	1
valid_sources[0x25]	2634	1			T2	25		T5	5		T8	4
valid_sources[0x26]	4249	1			T2	13		T5	6		T7	66
valid_sources[0x27]	2549	1			T2	14		T5	9		T6	6
valid_sources[0x28]	2477	1			T2	7		T6	4		T9	7
valid_sources[0x29]	2325	1			T2	11		T5	1		T6	4
valid_sources[0x2a]	2528	1			T2	6		T5	5		T8	7
valid_sources[0x2b]	2482	1			T2	2		T5	8		T7	207
valid_sources[0x2c]	4674	1			T2	7		T6	11		T8	4
valid_sources[0x2d]	3198	1			T2	6		T13	44		T105	2
valid_sources[0x2e]	2435	1			T2	6		T5	12		T6	1
valid_sources[0x2f]	7087	1			T2	9		T6	1		T7	1597
valid_sources[0x30]	3137	1			T2	2		T6	4		T9	1
valid_sources[0x31]	3719	1			T2	13		T5	1		T6	8
valid_sources[0x32]	7207	1			T2	11		T5	17		T6	6
valid_sources[0x33]	2299	1			T2	2		T5	4		T9	2
valid_sources[0x34]	3318	1			T2	11		T5	4		T9	2
valid_sources[0x35]	2374	1			T2	20		T5	4		T6	4
valid_sources[0x36]	2662	1			T2	21		T5	2		T7	160
valid_sources[0x37]	3493	1			T2	10		T5	5		T6	2
valid_sources[0x38]	2409	1			T2	13		T7	36		T8	14
valid_sources[0x39]	3621	1			T2	24		T5	2		T6	1
valid_sources[0x3a]	2545	1			T2	9		T5	3		T6	2
valid_sources[0x3b]	2423	1			T2	10		T8	3		T9	2
valid_sources[0x3c]	2520	1			T2	16		T5	1		T8	3
valid_sources[0x3d]	2703	1			T2	18		T5	1		T8	2
valid_sources[0x3e]	2513	1			T2	15		T5	2		T6	1
valid_sources[0x3f]	2430	1			T2	7		T5	2		T8	9
valid_sources[0x40]	3571	1			T2	18		T5	2		T13	53
valid_sources[0x41]	2390	1			T2	7		T6	2		T7	12
valid_sources[0x42]	2662	1			T2	11		T5	5		T7	11
valid_sources[0x43]	2652	1			T2	4		T6	2		T8	4
valid_sources[0x44]	2879	1			T2	7		T4	1		T5	13
valid_sources[0x45]	2849	1			T2	16		T6	1		T9	1
valid_sources[0x46]	2373	1			T2	12		T5	2		T7	22
valid_sources[0x47]	2489	1			T2	7		T5	7		T6	1
valid_sources[0x48]	5732	1			T2	12		T6	2		T7	25
valid_sources[0x49]	3660	1			T2	12		T8	6		T13	26
valid_sources[0x4a]	2451	1			T2	19		T5	5		T13	14
valid_sources[0x4b]	3385	1			T2	7		T6	8		T8	1
valid_sources[0x4c]	2218	1			T2	22		T6	1		T7	24
valid_sources[0x4d]	3312	1			T2	7		T5	6		T6	7
valid_sources[0x4e]	2526	1			T2	14		T5	6		T8	3
valid_sources[0x4f]	2442	1			T2	9		T6	1		T7	11
valid_sources[0x50]	2768	1			T2	3		T6	4		T8	6
valid_sources[0x51]	2299	1			T2	8		T5	1		T6	2
valid_sources[0x52]	2247	1			T2	9		T7	1		T8	6
valid_sources[0x53]	2488	1			T2	17		T5	3		T6	1
valid_sources[0x54]	2398	1			T2	6		T5	1		T8	1
valid_sources[0x55]	2122	1			T2	14		T5	2		T8	3
valid_sources[0x56]	3373	1			T2	14		T7	12		T12	2
valid_sources[0x57]	2453	1			T2	27		T9	2		T75	6
valid_sources[0x58]	2717	1			T2	20		T6	6		T8	1
valid_sources[0x59]	2454	1			T2	18		T5	3		T8	5
valid_sources[0x5a]	3394	1			T2	22		T5	13		T6	2
valid_sources[0x5b]	2711	1			T2	14		T6	9		T7	14
valid_sources[0x5c]	2329	1			T2	6		T7	13		T9	2
valid_sources[0x5d]	3281	1			T2	13		T5	12		T6	8
valid_sources[0x5e]	2319	1			T2	6		T5	16		T6	1
valid_sources[0x5f]	2437	1			T2	4		T5	1		T6	5
valid_sources[0x60]	3135	1			T2	15		T6	4		T8	5
valid_sources[0x61]	2322	1			T2	6		T5	5		T6	1
valid_sources[0x62]	2926	1			T2	11		T5	9		T9	2
valid_sources[0x63]	2226	1			T2	25		T5	2		T6	3
valid_sources[0x64]	2825	1			T2	11		T5	1		T6	1
valid_sources[0x65]	3364	1			T2	8		T5	5		T7	472
valid_sources[0x66]	3010	1			T2	8		T5	4		T6	1
valid_sources[0x67]	2512	1			T2	3		T5	1		T6	1
valid_sources[0x68]	2122	1			T2	5		T5	3		T6	3
valid_sources[0x69]	2503	1			T2	13		T9	5		T13	80
valid_sources[0x6a]	2359	1			T2	12		T7	12		T8	13
valid_sources[0x6b]	2313	1			T2	6		T5	2		T7	14
valid_sources[0x6c]	3882	1			T2	10		T7	13		T8	1
valid_sources[0x6d]	4471	1			T2	11		T6	5		T8	2
valid_sources[0x6e]	2692	1			T2	3		T5	2		T6	1
valid_sources[0x6f]	2626	1			T2	19		T9	9		T13	72
valid_sources[0x70]	2487	1			T2	4		T6	7		T7	11
valid_sources[0x71]	2467	1			T2	8		T5	3		T8	3
valid_sources[0x72]	2253	1			T2	10		T7	11		T9	2
valid_sources[0x73]	2491	1			T2	9		T5	3		T8	1
valid_sources[0x74]	2681	1			T2	13		T5	2		T6	9
valid_sources[0x75]	2306	1			T2	16		T6	4		T8	3
valid_sources[0x76]	2745	1			T2	12		T5	3		T6	2
valid_sources[0x77]	2336	1			T2	18		T5	1		T6	9
valid_sources[0x78]	2446	1			T2	10		T7	24		T8	2
valid_sources[0x79]	3347	1			T2	3		T5	10		T6	16
valid_sources[0x7a]	2368	1			T2	3		T7	13		T9	3
valid_sources[0x7b]	2595	1			T2	5		T6	6		T8	5
valid_sources[0x7c]	2265	1			T2	3		T6	2		T8	2
valid_sources[0x7d]	2330	1			T2	9		T5	2		T9	3
valid_sources[0x7e]	2491	1			T2	7		T5	6		T7	12
valid_sources[0x7f]	2428	1			T2	12		T8	10		T9	5
valid_sources[0x80]	2673	1			T2	14		T6	3		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

108340

1

T2

358

T3

1

T5

85

values[0x0]

all_enables

biggest_size

64300

1

T2

257

T5

72

T6

82

values[0x1]

all_enables

biggest_size

35464

1

T2

127

T5

46

T6

49