SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35261 | 1 | T5 | 306 | T6 | 290 | T8 | 303 | ||||
others[1] | 34879 | 1 | T5 | 309 | T6 | 317 | T8 | 291 | ||||
others[2] | 34955 | 1 | T5 | 273 | T6 | 307 | T8 | 291 | ||||
others[3] | 58297 | 1 | T5 | 514 | T6 | 483 | T8 | 516 | ||||
false | 18870 | 1 | T2 | 52 | T5 | 50 | T6 | 50 | ||||
true | 29009 | 1 | T1 | 2 | T2 | 73 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35116 | 1 | T5 | 327 | T6 | 301 | T8 | 306 | ||||
others[1] | 34936 | 1 | T5 | 304 | T6 | 298 | T8 | 279 | ||||
others[2] | 34975 | 1 | T5 | 298 | T6 | 281 | T8 | 309 | ||||
others[3] | 58531 | 1 | T5 | 472 | T6 | 501 | T8 | 512 | ||||
false | 12037 | 1 | T2 | 26 | T5 | 50 | T6 | 50 | ||||
true | 22238 | 1 | T1 | 2 | T2 | 47 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 735 | 1 | T2 | 1 | T7 | 9 | T12 | 1 | ||||
others[1] | 709 | 1 | T7 | 15 | T13 | 5 | T19 | 8 | ||||
others[2] | 713 | 1 | T7 | 7 | T12 | 1 | T13 | 8 | ||||
others[3] | 1148 | 1 | T2 | 1 | T7 | 23 | T13 | 14 | ||||
false | 14058 | 1 | T1 | 2 | T2 | 34 | T3 | 5 | ||||
true | 4244 | 1 | T2 | 11 | T7 | 119 | T12 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |