Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23987049	6111	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23987049	250671	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23987049	9711624	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23987049	250658	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23987049	6111	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23987049	250671	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23987049	9711624	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23987049	250658	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	6111	0	0
T2	60736	15	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	21	0	0
T6	54667	25	0	0
T7	293033	79	0	0
T8	54666	22	0	0
T9	16532	21	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	100	0	0
T19	0	17	0	0
T74	0	1	0	0
T75	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	250671	0	0
T2	60736	353	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	422	0	0
T6	54667	1328	0	0
T7	293033	2029	0	0
T8	54666	1265	0	0
T9	16532	568	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	2167	0	0
T19	0	309	0	0
T74	0	13	0	0
T75	0	30	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	9711624	0	0
T2	60736	27202	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	12161	0	0
T6	54667	29032	0	0
T7	293033	122190	0	0
T8	54666	25241	0	0
T9	16532	7330	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	118212	0	0
T73	0	459	0	0
T74	0	835	0	0
T75	0	6166	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	250658	0	0
T2	60736	353	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	422	0	0
T6	54667	1328	0	0
T7	293033	2023	0	0
T8	54666	1262	0	0
T9	16532	568	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	2167	0	0
T19	0	309	0	0
T74	0	13	0	0
T75	0	30	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	6111	0	0
T2	60736	15	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	21	0	0
T6	54667	25	0	0
T7	293033	79	0	0
T8	54666	22	0	0
T9	16532	21	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	100	0	0
T19	0	17	0	0
T74	0	1	0	0
T75	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	250671	0	0
T2	60736	353	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	422	0	0
T6	54667	1328	0	0
T7	293033	2029	0	0
T8	54666	1265	0	0
T9	16532	568	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	2167	0	0
T19	0	309	0	0
T74	0	13	0	0
T75	0	30	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	9711624	0	0
T2	60736	27202	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	12161	0	0
T6	54667	29032	0	0
T7	293033	122190	0	0
T8	54666	25241	0	0
T9	16532	7330	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	118212	0	0
T73	0	459	0	0
T74	0	835	0	0
T75	0	6166	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	250658	0	0
T2	60736	353	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	422	0	0
T6	54667	1328	0	0
T7	293033	2023	0	0
T8	54666	1262	0	0
T9	16532	568	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	2167	0	0
T19	0	309	0	0
T74	0	13	0	0
T75	0	30	0	0