Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24563203	16758	0	0
intr_enable_rd_A	24563203	34710	0	0
reset_en_rd_A	24563203	1814	0	0
reset_en_regwen_rd_A	24563203	1459	0	0
wake_info_capture_dis_rd_A	24563203	1309	0	0
wakeup_en_rd_A	24563203	2719	0	0
wakeup_en_regwen_rd_A	24563203	1377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	16758	0	0
T7	293033	8	0	0
T8	54666	0	0	0
T9	16532	0	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	268793	12	0	0
T14	2907	0	0	0
T19	0	6	0	0
T33	2194	0	0	0
T45	0	2	0	0
T66	0	8	0	0
T67	0	17	0	0
T73	3175	0	0	0
T83	1153	0	0	0
T85	0	12	0	0
T133	0	7	0	0
T134	0	42	0	0
T135	0	119	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	34710	0	0
T5	24620	126	0	0
T6	54667	0	0	0
T7	293033	1713	0	0
T8	54666	103	0	0
T9	16532	0	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	268793	0	0	0
T34	0	63	0	0
T51	0	2	0	0
T73	3175	0	0	0
T76	0	13	0	0
T83	1153	0	0	0
T106	0	412	0	0
T128	0	255	0	0
T136	0	123	0	0
T137	0	45	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	1814	0	0
T27	573452	23	0	0
T28	1233	0	0	0
T29	2840	0	0	0
T30	637	0	0	0
T48	0	26	0	0
T64	0	1	0	0
T80	0	21	0	0
T84	0	9	0	0
T123	0	31	0	0
T125	0	15	0	0
T138	0	4	0	0
T139	0	32	0	0
T140	0	18	0	0
T141	1808	0	0	0
T142	5345	0	0	0
T143	14320	0	0	0
T144	20266	0	0	0
T145	143697	0	0	0
T146	13164	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	1459	0	0
T27	0	25	0	0
T48	0	37	0	0
T64	0	6	0	0
T67	390776	9	0	0
T80	0	3	0	0
T84	0	5	0	0
T109	29173	0	0	0
T123	0	26	0	0
T125	0	29	0	0
T133	132142	0	0	0
T139	0	19	0	0
T140	0	13	0	0
T147	5954	0	0	0
T148	8152	0	0	0
T149	4155	0	0	0
T150	861	0	0	0
T151	1070	0	0	0
T152	4594	0	0	0
T153	2209	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	1309	0	0
T27	0	11	0	0
T48	0	24	0	0
T64	0	5	0	0
T67	390776	2	0	0
T80	0	7	0	0
T84	0	16	0	0
T109	29173	0	0	0
T123	0	26	0	0
T125	0	1	0	0
T133	132142	0	0	0
T139	0	21	0	0
T140	0	14	0	0
T147	5954	0	0	0
T148	8152	0	0	0
T149	4155	0	0	0
T150	861	0	0	0
T151	1070	0	0	0
T152	4594	0	0	0
T153	2209	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	2719	0	0
T27	0	5	0	0
T48	0	5	0	0
T64	0	3	0	0
T67	390776	6	0	0
T80	0	16	0	0
T84	0	8	0	0
T109	29173	0	0	0
T123	0	10	0	0
T125	0	14	0	0
T133	132142	0	0	0
T139	0	9	0	0
T140	0	9	0	0
T147	5954	0	0	0
T148	8152	0	0	0
T149	4155	0	0	0
T150	861	0	0	0
T151	1070	0	0	0
T152	4594	0	0	0
T153	2209	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563203	1377	0	0
T27	0	7	0	0
T48	0	21	0	0
T67	390776	5	0	0
T80	0	9	0	0
T84	0	7	0	0
T109	29173	0	0	0
T123	0	16	0	0
T133	132142	0	0	0
T138	0	2	0	0
T139	0	21	0	0
T140	0	29	0	0
T147	5954	0	0	0
T148	8152	0	0	0
T149	4155	0	0	0
T150	861	0	0	0
T151	1070	0	0	0
T152	4594	0	0	0
T153	2209	0	0	0
T154	0	3	0	0