Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71961147	148404	0	0
StatusRise_A	71961147	165501	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71961147	148404	0	0
T2	182208	582	0	0
T3	3411	0	0	0
T4	3501	3	0	0
T5	73860	216	0	0
T6	164001	221	0	0
T7	879099	2541	0	0
T8	163998	213	0	0
T9	49596	226	0	0
T10	44937	3	0	0
T12	19125	54	0	0
T13	0	3232	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71961147	165501	0	0
T1	3561	6	0	0
T2	182208	637	0	0
T3	3411	15	0	0
T4	3501	9	0	0
T5	73860	218	0	0
T6	164001	223	0	0
T7	879099	2847	0	0
T8	163998	219	0	0
T9	49596	232	0	0
T10	44937	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23987049	55030	0	0
StatusRise_A	23987049	61215	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	55030	0	0
T2	60736	216	0	0
T3	1137	0	0	0
T4	1167	1	0	0
T5	24620	86	0	0
T6	54667	89	0	0
T7	293033	919	0	0
T8	54666	83	0	0
T9	16532	85	0	0
T10	14979	1	0	0
T12	6375	18	0	0
T13	0	1196	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	61215	0	0
T1	1187	2	0	0
T2	60736	237	0	0
T3	1137	5	0	0
T4	1167	3	0	0
T5	24620	87	0	0
T6	54667	90	0	0
T7	293033	1031	0	0
T8	54666	85	0	0
T9	16532	87	0	0
T10	14979	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23987049	55030	0	0
StatusRise_A	23987049	61216	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	55030	0	0
T2	60736	216	0	0
T3	1137	0	0	0
T4	1167	1	0	0
T5	24620	86	0	0
T6	54667	89	0	0
T7	293033	919	0	0
T8	54666	83	0	0
T9	16532	85	0	0
T10	14979	1	0	0
T12	6375	18	0	0
T13	0	1196	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	61216	0	0
T1	1187	2	0	0
T2	60736	237	0	0
T3	1137	5	0	0
T4	1167	3	0	0
T5	24620	87	0	0
T6	54667	90	0	0
T7	293033	1031	0	0
T8	54666	85	0	0
T9	16532	87	0	0
T10	14979	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23987049	38344	0	0
StatusRise_A	23987049	43070	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	38344	0	0
T2	60736	150	0	0
T3	1137	0	0	0
T4	1167	1	0	0
T5	24620	44	0	0
T6	54667	43	0	0
T7	293033	703	0	0
T8	54666	47	0	0
T9	16532	56	0	0
T10	14979	1	0	0
T12	6375	18	0	0
T13	0	840	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	43070	0	0
T1	1187	2	0	0
T2	60736	163	0	0
T3	1137	5	0	0
T4	1167	3	0	0
T5	24620	44	0	0
T6	54667	43	0	0
T7	293033	785	0	0
T8	54666	49	0	0
T9	16532	58	0	0
T10	14979	2	0	0