Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23987634	6431	0	0
EscTimeoutStoppedByClReset_A	23987049	3414504	0	0
EscTimeoutTriggersReset_A	5127006	307	0	0
RomAllowActiveState_A	23987049	60831	0	0
RomAllowCheckGoodState_A	23987049	60882	0	0
RomBlockActiveState_A	23987049	32613	0	0
RomBlockCheckGoodState_A	23987049	425876	0	0
RomIntgChkDisFalse_A	23987049	23293820	0	0
RomIntgChkDisTrue_A	23987049	161207	0	0
RstreqChkEsctimeout_A	23987049	4641	0	0
RstreqChkFsmterm_A	23987049	180	0	0
RstreqChkGlbesc_A	23987049	4641	0	0
RstreqChkMainpd_A	23987049	983671	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987634	6431	0	0
T10	14980	22	0	0
T11	0	229	0	0
T12	6375	0	0	0
T13	268794	0	0	0
T14	2908	0	0	0
T31	7837	0	0	0
T33	2195	0	0	0
T73	3175	0	0	0
T74	1104	0	0	0
T75	10526	0	0	0
T83	1154	0	0	0
T155	0	122	0	0
T156	0	251	0	0
T157	0	40	0	0
T158	0	55	0	0
T159	0	32	0	0
T160	0	217	0	0
T161	0	5	0	0
T162	0	15	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	3414504	0	0
T1	1187	27	0	0
T2	60736	8763	0	0
T3	1137	41	0	0
T4	1167	49	0	0
T5	24620	3428	0	0
T6	54667	9785	0	0
T7	293033	26352	0	0
T8	54666	11260	0	0
T9	16532	3504	0	0
T10	14979	23	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5127006	307	0	0
T4	216	3	0	0
T5	8879	0	0	0
T6	5695	0	0	0
T7	101426	0	0	0
T8	6142	0	0	0
T9	7425	0	0	0
T10	1582	3	0	0
T11	0	3	0	0
T12	493	0	0	0
T13	149236	0	0	0
T83	596	0	0	0
T155	0	3	0	0
T156	0	3	0	0
T157	0	3	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	7	0	0
T166	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	60831	0	0
T1	1187	2	0	0
T2	60736	237	0	0
T3	1137	5	0	0
T4	1167	3	0	0
T5	24620	87	0	0
T6	54667	90	0	0
T7	293033	1031	0	0
T8	54666	85	0	0
T9	16532	87	0	0
T10	14979	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	60882	0	0
T1	1187	2	0	0
T2	60736	237	0	0
T3	1137	5	0	0
T4	1167	3	0	0
T5	24620	87	0	0
T6	54667	90	0	0
T7	293033	1031	0	0
T8	54666	85	0	0
T9	16532	87	0	0
T10	14979	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	32613	0	0
T5	24620	7	0	0
T6	54667	0	0	0
T7	293033	0	0	0
T8	54666	0	0	0
T9	16532	0	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	268793	0	0	0
T40	0	464	0	0
T41	0	1130	0	0
T73	3175	0	0	0
T83	1153	0	0	0
T147	0	894	0	0
T167	0	655	0	0
T168	0	11	0	0
T169	0	254	0	0
T170	0	39	0	0
T171	0	192	0	0
T172	0	528	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	425876	0	0
T2	60736	596	0	0
T3	1137	0	0	0
T4	1167	0	0	0
T5	24620	1328	0	0
T6	54667	4250	0	0
T7	293033	2933	0	0
T8	54666	4026	0	0
T9	16532	1234	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	0	3829	0	0
T19	0	460	0	0
T75	0	228	0	0
T137	0	229	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	23293820	0	0
T1	1187	1057	0	0
T2	60736	59081	0	0
T3	1137	814	0	0
T4	1167	1038	0	0
T5	24620	24174	0	0
T6	54667	19607	0	0
T7	293033	284520	0	0
T8	54666	52716	0	0
T9	16532	15783	0	0
T10	14979	14917	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	161207	0	0
T5	24620	382	0	0
T6	54667	34983	0	0
T7	293033	0	0	0
T8	54666	1807	0	0
T9	16532	597	0	0
T10	14979	0	0	0
T12	6375	0	0	0
T13	268793	0	0	0
T40	0	1305	0	0
T41	0	2130	0	0
T73	3175	0	0	0
T83	1153	0	0	0
T169	0	900	0	0
T173	0	561	0	0
T174	0	3103	0	0
T175	0	1841	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	4641	0	0
T2	60736	7	0	0
T3	1137	0	0	0
T4	1167	1	0	0
T5	24620	0	0	0
T6	54667	0	0	0
T7	293033	107	0	0
T8	54666	0	0	0
T9	16532	0	0	0
T10	14979	1	0	0
T11	0	1	0	0
T12	6375	8	0	0
T13	0	89	0	0
T31	0	5	0	0
T32	0	5	0	0
T33	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	180	0	0
T16	17004	40	0	0
T17	0	40	0	0
T18	0	40	0	0
T20	0	40	0	0
T21	0	20	0	0
T22	4355	0	0	0
T23	864	0	0	0
T24	4199	0	0	0
T25	5335	0	0	0
T26	1098	0	0	0
T27	573452	0	0	0
T28	1233	0	0	0
T29	2840	0	0	0
T30	637	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	4641	0	0
T2	60736	7	0	0
T3	1137	0	0	0
T4	1167	1	0	0
T5	24620	0	0	0
T6	54667	0	0	0
T7	293033	107	0	0
T8	54666	0	0	0
T9	16532	0	0	0
T10	14979	1	0	0
T11	0	1	0	0
T12	6375	8	0	0
T13	0	89	0	0
T31	0	5	0	0
T32	0	5	0	0
T33	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23987049	983671	0	0
T1	1187	6	0	0
T2	60736	1317	0	0
T3	1137	22	0	0
T4	1167	0	0	0
T5	24620	1141	0	0
T6	54667	4841	0	0
T7	293033	7296	0	0
T8	54666	4280	0	0
T9	16532	1880	0	0
T10	14979	0	0	0
T12	0	622	0	0
T13	0	5255	0	0