Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13295 |
1 |
|
|
T2 |
23 |
|
T4 |
13 |
|
T5 |
3 |
auto[1] |
15924 |
1 |
|
|
T2 |
27 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13724 |
1 |
|
|
T2 |
26 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
15495 |
1 |
|
|
T2 |
24 |
|
T4 |
15 |
|
T5 |
2 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1878 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[0] |
auto[0] |
auto[1] |
1842 |
1 |
|
|
T4 |
2 |
|
T83 |
2 |
|
T38 |
5 |
auto[0] |
auto[1] |
auto[0] |
4973 |
1 |
|
|
T2 |
13 |
|
T4 |
4 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
4602 |
1 |
|
|
T2 |
10 |
|
T4 |
4 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1723 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
2528 |
1 |
|
|
T4 |
5 |
|
T5 |
1 |
|
T38 |
3 |
auto[1] |
auto[1] |
auto[0] |
5150 |
1 |
|
|
T2 |
13 |
|
T4 |
4 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
6523 |
1 |
|
|
T2 |
14 |
|
T4 |
4 |
|
T6 |
16 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13157 |
1 |
|
|
T2 |
19 |
|
T4 |
8 |
|
T5 |
6 |
auto[1] |
16062 |
1 |
|
|
T2 |
31 |
|
T4 |
21 |
|
T5 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13877 |
1 |
|
|
T2 |
19 |
|
T4 |
17 |
|
T5 |
4 |
auto[1] |
15342 |
1 |
|
|
T2 |
31 |
|
T4 |
12 |
|
T5 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1903 |
1 |
|
|
T4 |
1 |
|
T5 |
3 |
|
T38 |
6 |
auto[0] |
auto[0] |
auto[1] |
1803 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T83 |
2 |
auto[0] |
auto[1] |
auto[0] |
4871 |
1 |
|
|
T2 |
7 |
|
T4 |
4 |
|
T6 |
12 |
auto[0] |
auto[1] |
auto[1] |
4580 |
1 |
|
|
T2 |
12 |
|
T4 |
2 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[0] |
1792 |
1 |
|
|
T4 |
6 |
|
T83 |
1 |
|
T38 |
2 |
auto[1] |
auto[0] |
auto[1] |
2473 |
1 |
|
|
T4 |
5 |
|
T10 |
1 |
|
T38 |
2 |
auto[1] |
auto[1] |
auto[0] |
5311 |
1 |
|
|
T2 |
12 |
|
T4 |
6 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
6486 |
1 |
|
|
T2 |
19 |
|
T4 |
4 |
|
T6 |
14 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13070 |
1 |
|
|
T2 |
20 |
|
T4 |
9 |
|
T5 |
4 |
auto[1] |
16149 |
1 |
|
|
T2 |
30 |
|
T4 |
20 |
|
T5 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13754 |
1 |
|
|
T2 |
29 |
|
T4 |
14 |
|
T5 |
2 |
auto[1] |
15465 |
1 |
|
|
T2 |
21 |
|
T4 |
15 |
|
T5 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1766 |
1 |
|
|
T4 |
2 |
|
T38 |
5 |
|
T39 |
6 |
auto[0] |
auto[0] |
auto[1] |
1880 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[0] |
4891 |
1 |
|
|
T2 |
12 |
|
T4 |
2 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
4533 |
1 |
|
|
T2 |
8 |
|
T4 |
4 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1865 |
1 |
|
|
T4 |
4 |
|
T10 |
1 |
|
T83 |
2 |
auto[1] |
auto[0] |
auto[1] |
2460 |
1 |
|
|
T4 |
6 |
|
T5 |
1 |
|
T83 |
1 |
auto[1] |
auto[1] |
auto[0] |
5232 |
1 |
|
|
T2 |
17 |
|
T4 |
6 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
6592 |
1 |
|
|
T2 |
13 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13231 |
1 |
|
|
T2 |
18 |
|
T4 |
13 |
|
T5 |
4 |
auto[1] |
15988 |
1 |
|
|
T2 |
32 |
|
T4 |
16 |
|
T5 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13959 |
1 |
|
|
T2 |
22 |
|
T4 |
10 |
|
T5 |
6 |
auto[1] |
15260 |
1 |
|
|
T2 |
28 |
|
T4 |
19 |
|
T5 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1882 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T38 |
6 |
auto[0] |
auto[0] |
auto[1] |
1835 |
1 |
|
|
T4 |
5 |
|
T38 |
5 |
|
T39 |
5 |
auto[0] |
auto[1] |
auto[0] |
4997 |
1 |
|
|
T2 |
9 |
|
T4 |
3 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[1] |
4517 |
1 |
|
|
T2 |
9 |
|
T4 |
3 |
|
T6 |
11 |
auto[1] |
auto[0] |
auto[0] |
1832 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
2422 |
1 |
|
|
T4 |
3 |
|
T10 |
1 |
|
T83 |
2 |
auto[1] |
auto[1] |
auto[0] |
5248 |
1 |
|
|
T2 |
13 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
6486 |
1 |
|
|
T2 |
19 |
|
T4 |
8 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13133 |
1 |
|
|
T2 |
21 |
|
T4 |
13 |
|
T5 |
2 |
auto[1] |
16086 |
1 |
|
|
T2 |
29 |
|
T4 |
16 |
|
T5 |
5 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13884 |
1 |
|
|
T2 |
24 |
|
T4 |
9 |
|
T5 |
3 |
auto[1] |
15335 |
1 |
|
|
T2 |
26 |
|
T4 |
20 |
|
T5 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1874 |
1 |
|
|
T4 |
3 |
|
T38 |
2 |
|
T39 |
8 |
auto[0] |
auto[0] |
auto[1] |
1872 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[0] |
4949 |
1 |
|
|
T2 |
10 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
4438 |
1 |
|
|
T2 |
11 |
|
T4 |
5 |
|
T6 |
12 |
auto[1] |
auto[0] |
auto[0] |
1736 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
2489 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T83 |
1 |
auto[1] |
auto[1] |
auto[0] |
5325 |
1 |
|
|
T2 |
14 |
|
T4 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
6536 |
1 |
|
|
T2 |
15 |
|
T4 |
7 |
|
T5 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7971 |
1 |
|
|
T4 |
13 |
|
T5 |
3 |
|
T10 |
2 |
auto[1] |
21248 |
1 |
|
|
T2 |
50 |
|
T4 |
16 |
|
T5 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13312 |
1 |
|
|
T2 |
27 |
|
T4 |
12 |
|
T5 |
1 |
auto[1] |
15907 |
1 |
|
|
T2 |
23 |
|
T4 |
17 |
|
T5 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13940 |
1 |
|
|
T2 |
19 |
|
T4 |
15 |
|
T5 |
4 |
auto[1] |
15279 |
1 |
|
|
T2 |
31 |
|
T4 |
14 |
|
T5 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1906 |
1 |
|
|
T4 |
4 |
|
T38 |
3 |
|
T39 |
6 |
auto[0] |
auto[0] |
auto[1] |
1828 |
1 |
|
|
T4 |
2 |
|
T10 |
1 |
|
T83 |
1 |
auto[0] |
auto[1] |
auto[0] |
4954 |
1 |
|
|
T2 |
12 |
|
T4 |
3 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
4624 |
1 |
|
|
T2 |
15 |
|
T4 |
3 |
|
T6 |
8 |
auto[1] |
auto[0] |
auto[0] |
1849 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
auto[1] |
2388 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T83 |
1 |
auto[1] |
auto[1] |
auto[0] |
5231 |
1 |
|
|
T2 |
7 |
|
T4 |
4 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
6439 |
1 |
|
|
T2 |
16 |
|
T4 |
6 |
|
T5 |
1 |