Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	542025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203737

1

T1

1

T2

206

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	389627	1			T1	1		T2	427		T3	26
values[0x0]	177479	1			T2	235		T3	8		T4	179
values[0x1]	178656	1			T2	217		T3	6		T4	189

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	428248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

317514

1

T1

1

T2

342

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2652	1			T2	4		T4	9		T5	1
valid_sources[0x01]	2625	1			T2	1		T4	4		T5	1
valid_sources[0x02]	2452	1			T2	1		T6	1		T8	1
valid_sources[0x03]	2201	1			T2	3		T4	25		T5	1
valid_sources[0x04]	2239	1			T2	3		T6	2		T25	1
valid_sources[0x05]	3129	1			T2	4		T83	2		T25	1
valid_sources[0x06]	3509	1			T2	2		T4	1		T6	5
valid_sources[0x07]	3239	1			T2	2		T4	1		T40	1
valid_sources[0x08]	4433	1			T2	3		T4	6		T5	1
valid_sources[0x09]	3205	1			T2	3		T5	3		T39	13
valid_sources[0x0a]	2709	1			T4	1		T39	7		T195	3
valid_sources[0x0b]	7098	1			T2	4		T6	1		T38	26
valid_sources[0x0c]	2740	1			T2	3		T4	9		T6	3
valid_sources[0x0d]	2414	1			T2	7		T6	4		T40	5
valid_sources[0x0e]	2340	1			T2	1		T6	6		T13	2
valid_sources[0x0f]	2375	1			T2	2		T6	4		T40	1
valid_sources[0x10]	2399	1			T2	1		T6	8		T8	1
valid_sources[0x11]	2737	1			T2	8		T5	4		T6	4
valid_sources[0x12]	2424	1			T2	2		T4	5		T6	1
valid_sources[0x13]	2278	1			T2	4		T8	1		T37	1
valid_sources[0x14]	2434	1			T2	2		T4	4		T6	1
valid_sources[0x15]	2643	1			T2	4		T82	1		T39	5
valid_sources[0x16]	3721	1			T2	3		T6	1		T39	8
valid_sources[0x17]	2670	1			T2	5		T4	2		T6	11
valid_sources[0x18]	3149	1			T40	2		T38	9		T39	9
valid_sources[0x19]	2553	1			T2	2		T5	1		T6	9
valid_sources[0x1a]	2536	1			T2	4		T6	2		T8	2
valid_sources[0x1b]	2239	1			T2	5		T6	11		T13	1
valid_sources[0x1c]	2228	1			T2	3		T5	3		T40	3
valid_sources[0x1d]	2511	1			T4	22		T6	3		T82	1
valid_sources[0x1e]	2317	1			T2	3		T4	11		T5	1
valid_sources[0x1f]	3214	1			T2	6		T4	5		T6	10
valid_sources[0x20]	2635	1			T2	1		T6	4		T37	1
valid_sources[0x21]	3554	1			T2	3		T3	40		T5	3
valid_sources[0x22]	2376	1			T2	6		T6	4		T8	1
valid_sources[0x23]	2820	1			T2	5		T6	2		T40	1
valid_sources[0x24]	3680	1			T2	2		T13	1		T39	7
valid_sources[0x25]	2356	1			T2	5		T6	4		T8	1
valid_sources[0x26]	5722	1			T2	4		T6	5		T38	1
valid_sources[0x27]	2973	1			T2	2		T4	8		T40	1
valid_sources[0x28]	3422	1			T2	4		T6	9		T83	1
valid_sources[0x29]	2374	1			T2	4		T4	9		T8	1
valid_sources[0x2a]	2337	1			T2	2		T4	1		T25	1
valid_sources[0x2b]	2405	1			T2	3		T5	1		T83	2
valid_sources[0x2c]	2200	1			T2	8		T6	8		T40	5
valid_sources[0x2d]	2535	1			T4	1		T81	26		T82	1
valid_sources[0x2e]	2305	1			T2	7		T5	1		T40	1
valid_sources[0x2f]	2366	1			T2	5		T6	5		T13	1
valid_sources[0x30]	2634	1			T2	1		T6	6		T40	5
valid_sources[0x31]	2448	1			T2	5		T25	3		T39	8
valid_sources[0x32]	2514	1			T2	5		T4	6		T5	1
valid_sources[0x33]	3403	1			T2	4		T8	3		T39	8
valid_sources[0x34]	5819	1			T2	3		T4	5		T6	12
valid_sources[0x35]	5435	1			T2	4		T6	12		T8	1
valid_sources[0x36]	4217	1			T2	4		T6	18		T40	1
valid_sources[0x37]	3414	1			T2	1		T5	1		T40	1
valid_sources[0x38]	2618	1			T2	2		T5	2		T37	7
valid_sources[0x39]	2379	1			T2	4		T4	3		T6	9
valid_sources[0x3a]	2309	1			T2	3		T4	3		T5	2
valid_sources[0x3b]	2435	1			T2	2		T4	1		T13	1
valid_sources[0x3c]	2625	1			T2	9		T4	11		T6	3
valid_sources[0x3d]	2662	1			T2	2		T4	1		T5	1
valid_sources[0x3e]	2524	1			T2	2		T4	3		T8	1
valid_sources[0x3f]	2688	1			T2	4		T6	5		T8	1
valid_sources[0x40]	2308	1			T2	4		T4	12		T5	1
valid_sources[0x41]	2671	1			T2	2		T40	2		T25	1
valid_sources[0x42]	2234	1			T2	2		T6	9		T39	7
valid_sources[0x43]	2735	1			T2	3		T4	10		T8	1
valid_sources[0x44]	3397	1			T2	1		T4	8		T40	2
valid_sources[0x45]	2397	1			T2	6		T8	2		T40	1
valid_sources[0x46]	3033	1			T2	7		T6	3		T40	1
valid_sources[0x47]	3181	1			T2	4		T4	9		T6	3
valid_sources[0x48]	3262	1			T2	5		T4	4		T6	3
valid_sources[0x49]	2419	1			T2	4		T6	5		T40	1
valid_sources[0x4a]	3536	1			T2	3		T24	872		T37	1
valid_sources[0x4b]	2472	1			T2	4		T4	16		T37	1
valid_sources[0x4c]	2482	1			T2	4		T6	3		T37	9
valid_sources[0x4d]	2191	1			T2	3		T5	1		T40	4
valid_sources[0x4e]	3214	1			T2	5		T4	8		T5	1
valid_sources[0x4f]	4624	1			T2	1		T39	7		T179	3
valid_sources[0x50]	3365	1			T2	3		T4	1		T13	1
valid_sources[0x51]	3458	1			T2	1		T13	1		T14	5
valid_sources[0x52]	2162	1			T4	13		T5	2		T6	8
valid_sources[0x53]	2612	1			T4	11		T5	1		T6	6
valid_sources[0x54]	2356	1			T2	1		T4	13		T8	1
valid_sources[0x55]	2303	1			T2	5		T4	1		T39	8
valid_sources[0x56]	3222	1			T2	4		T4	4		T8	1
valid_sources[0x57]	2216	1			T2	1		T5	1		T6	2
valid_sources[0x58]	2726	1			T2	2		T4	14		T6	2
valid_sources[0x59]	2317	1			T2	2		T4	1		T6	15
valid_sources[0x5a]	2265	1			T2	4		T4	6		T5	1
valid_sources[0x5b]	2314	1			T2	1		T4	15		T40	2
valid_sources[0x5c]	2678	1			T2	3		T4	7		T40	1
valid_sources[0x5d]	2620	1			T2	4		T6	2		T83	1
valid_sources[0x5e]	2533	1			T2	8		T6	5		T39	8
valid_sources[0x5f]	2425	1			T2	2		T40	3		T25	1
valid_sources[0x60]	3091	1			T2	4		T5	1		T6	3
valid_sources[0x61]	2371	1			T2	3		T4	5		T5	2
valid_sources[0x62]	2255	1			T2	3		T13	2		T39	9
valid_sources[0x63]	2640	1			T2	3		T4	4		T6	2
valid_sources[0x64]	3068	1			T2	5		T14	14		T39	10
valid_sources[0x65]	4265	1			T2	5		T4	6		T6	8
valid_sources[0x66]	3127	1			T2	5		T4	2		T6	7
valid_sources[0x67]	2977	1			T2	2		T5	2		T39	14
valid_sources[0x68]	2360	1			T2	3		T4	1		T5	1
valid_sources[0x69]	2840	1			T2	1		T4	3		T6	9
valid_sources[0x6a]	2439	1			T2	6		T4	14		T5	1
valid_sources[0x6b]	2487	1			T2	3		T5	1		T6	4
valid_sources[0x6c]	2462	1			T39	7		T42	3		T84	3
valid_sources[0x6d]	2277	1			T4	5		T6	6		T8	1
valid_sources[0x6e]	2247	1			T2	8		T4	3		T5	1
valid_sources[0x6f]	2589	1			T2	6		T4	4		T5	1
valid_sources[0x70]	3632	1			T2	3		T4	2		T5	1
valid_sources[0x71]	2683	1			T2	5		T5	1		T6	1
valid_sources[0x72]	2446	1			T2	3		T5	1		T38	4
valid_sources[0x73]	2038	1			T4	6		T6	5		T40	1
valid_sources[0x74]	3522	1			T2	2		T5	1		T6	4
valid_sources[0x75]	2465	1			T2	4		T4	2		T5	1
valid_sources[0x76]	6099	1			T4	12		T44	11		T38	16
valid_sources[0x77]	2466	1			T2	1		T5	1		T6	2
valid_sources[0x78]	2677	1			T2	3		T4	18		T40	1
valid_sources[0x79]	2344	1			T2	1		T6	1		T8	1
valid_sources[0x7a]	4102	1			T2	2		T4	5		T6	1
valid_sources[0x7b]	2533	1			T2	1		T4	4		T5	1
valid_sources[0x7c]	2533	1			T2	2		T83	1		T13	1
valid_sources[0x7d]	2573	1			T2	1		T5	2		T6	12
valid_sources[0x7e]	3345	1			T2	5		T6	6		T40	2
valid_sources[0x7f]	3201	1			T2	2		T6	9		T8	1
valid_sources[0x80]	2794	1			T2	3		T4	1		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103273

1

T1

1

T2

93

T3

7

values[0x0]

all_enables

biggest_size

65247

1

T2

80

T3

1

T4

54

values[0x1]

all_enables

biggest_size

35217

1

T2

33

T3

1

T4

34