SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34416 | 1 | T2 | 278 | T6 | 400 | T7 | 395 | ||||
others[1] | 34517 | 1 | T2 | 296 | T6 | 383 | T7 | 389 | ||||
others[2] | 34966 | 1 | T2 | 300 | T6 | 400 | T7 | 423 | ||||
others[3] | 58087 | 1 | T2 | 533 | T6 | 672 | T7 | 650 | ||||
false | 20134 | 1 | T2 | 50 | T6 | 50 | T7 | 50 | ||||
true | 30449 | 1 | T1 | 1 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34608 | 1 | T2 | 289 | T6 | 426 | T7 | 383 | ||||
others[1] | 34747 | 1 | T2 | 303 | T6 | 421 | T7 | 421 | ||||
others[2] | 34683 | 1 | T2 | 303 | T6 | 398 | T7 | 402 | ||||
others[3] | 58059 | 1 | T2 | 505 | T6 | 644 | T7 | 659 | ||||
false | 12647 | 1 | T2 | 50 | T6 | 50 | T7 | 50 | ||||
true | 23022 | 1 | T1 | 1 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 658 | 1 | T3 | 1 | T40 | 4 | T38 | 1 | ||||
others[1] | 687 | 1 | T4 | 2 | T40 | 4 | T25 | 1 | ||||
others[2] | 747 | 1 | T4 | 1 | T40 | 8 | T25 | 1 | ||||
others[3] | 1162 | 1 | T40 | 7 | T25 | 1 | T38 | 3 | ||||
false | 14138 | 1 | T1 | 1 | T2 | 1 | T3 | 3 | ||||
true | 4188 | 1 | T3 | 1 | T4 | 9 | T8 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |