Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26477841	13664	0	0
intr_enable_rd_A	26477841	43939	0	0
reset_en_rd_A	26477841	1515	0	0
reset_en_regwen_rd_A	26477841	1204	0	0
wake_info_capture_dis_rd_A	26477841	1173	0	0
wakeup_en_rd_A	26477841	2214	0	0
wakeup_en_regwen_rd_A	26477841	1186	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	13664	0	0
T12	1210	0	0	0
T17	2200	0	0	0
T21	706765	16	0	0
T22	0	15	0	0
T23	0	18	0	0
T49	3226	0	0	0
T51	0	39	0	0
T54	0	34	0	0
T55	0	129	0	0
T74	0	9	0	0
T75	0	21	0	0
T101	0	12	0	0
T151	0	3	0	0
T152	35686	0	0	0
T153	15658	0	0	0
T154	1543	0	0	0
T155	1719	0	0	0
T156	2513	0	0	0
T157	21980	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	43939	0	0
T5	7563	18	0	0
T6	59776	0	0	0
T7	30512	0	0	0
T8	1465	0	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T24	50782	0	0	0
T25	0	25	0	0
T37	2062	0	0	0
T39	0	499	0	0
T40	7069	114	0	0
T83	2042	0	0	0
T86	0	251	0	0
T87	0	186	0	0
T148	0	379	0	0
T149	0	12	0	0
T158	0	54	0	0
T159	0	108	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	1515	0	0
T53	0	135	0	0
T54	627449	14	0	0
T55	583382	0	0	0
T57	0	23	0	0
T58	0	137	0	0
T90	0	3	0	0
T91	0	6	0	0
T94	7955	0	0	0
T95	14950	0	0	0
T96	56364	0	0	0
T97	2913	0	0	0
T98	2352	0	0	0
T99	297202	3	0	0
T100	1958	0	0	0
T160	0	7	0	0
T161	0	3	0	0
T162	0	2	0	0
T163	303488	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	1204	0	0
T54	627449	11	0	0
T55	583382	0	0	0
T57	0	16	0	0
T79	0	2	0	0
T90	0	4	0	0
T94	7955	0	0	0
T95	14950	0	0	0
T96	56364	0	0	0
T97	2913	0	0	0
T98	2352	0	0	0
T99	297202	4	0	0
T100	1958	0	0	0
T160	0	8	0	0
T161	0	2	0	0
T162	0	8	0	0
T163	303488	10	0	0
T164	0	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	1173	0	0
T53	0	65	0	0
T54	627449	11	0	0
T55	583382	0	0	0
T57	0	15	0	0
T58	0	75	0	0
T90	0	7	0	0
T94	7955	0	0	0
T95	14950	0	0	0
T96	56364	0	0	0
T97	2913	0	0	0
T98	2352	0	0	0
T99	297202	1	0	0
T100	1958	0	0	0
T129	0	8	0	0
T163	303488	6	0	0
T165	0	248	0	0
T166	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	2214	0	0
T53	0	235	0	0
T54	627449	13	0	0
T55	583382	0	0	0
T57	0	17	0	0
T58	0	285	0	0
T90	0	3	0	0
T94	7955	0	0	0
T95	14950	0	0	0
T96	56364	0	0	0
T97	2913	0	0	0
T98	2352	0	0	0
T99	297202	4	0	0
T100	1958	0	0	0
T129	0	5	0	0
T160	0	2	0	0
T161	0	12	0	0
T162	0	15	0	0
T163	303488	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26477841	1186	0	0
T53	0	70	0	0
T54	627449	16	0	0
T55	583382	0	0	0
T57	0	24	0	0
T58	0	67	0	0
T93	0	1	0	0
T94	7955	0	0	0
T95	14950	0	0	0
T96	56364	0	0	0
T97	2913	0	0	0
T98	2352	0	0	0
T99	297202	0	0	0
T100	1958	0	0	0
T129	0	2	0	0
T160	0	7	0	0
T161	0	10	0	0
T162	0	15	0	0
T163	303488	8	0	0