Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	77628132	153222	0	0
StatusRise_A	77628132	170775	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77628132	153222	0	0
T1	46533	3	0	0
T2	158835	199	0	0
T3	4581	9	0	0
T4	43620	159	0	0
T5	22689	16	0	0
T6	179328	200	0	0
T7	91536	227	0	0
T8	4395	12	0	0
T9	7950	6	0	0
T10	5907	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77628132	170775	0	0
T1	46533	6	0	0
T2	158835	201	0	0
T3	4581	12	0	0
T4	43620	178	0	0
T5	22689	19	0	0
T6	179328	206	0	0
T7	91536	232	0	0
T8	4395	15	0	0
T9	7950	9	0	0
T10	5907	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25876044	56935	0	0
StatusRise_A	25876044	63283	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	56935	0	0
T1	15511	1	0	0
T2	52945	79	0	0
T3	1527	3	0	0
T4	14540	58	0	0
T5	7563	7	0	0
T6	59776	80	0	0
T7	30512	87	0	0
T8	1465	4	0	0
T9	2650	2	0	0
T10	1969	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	63283	0	0
T1	15511	2	0	0
T2	52945	80	0	0
T3	1527	4	0	0
T4	14540	65	0	0
T5	7563	8	0	0
T6	59776	82	0	0
T7	30512	89	0	0
T8	1465	5	0	0
T9	2650	3	0	0
T10	1969	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25876044	56935	0	0
StatusRise_A	25876044	63283	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	56935	0	0
T1	15511	1	0	0
T2	52945	79	0	0
T3	1527	3	0	0
T4	14540	58	0	0
T5	7563	7	0	0
T6	59776	80	0	0
T7	30512	87	0	0
T8	1465	4	0	0
T9	2650	2	0	0
T10	1969	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	63283	0	0
T1	15511	2	0	0
T2	52945	80	0	0
T3	1527	4	0	0
T4	14540	65	0	0
T5	7563	8	0	0
T6	59776	82	0	0
T7	30512	89	0	0
T8	1465	5	0	0
T9	2650	3	0	0
T10	1969	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25876044	39352	0	0
StatusRise_A	25876044	44209	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	39352	0	0
T1	15511	1	0	0
T2	52945	41	0	0
T3	1527	3	0	0
T4	14540	43	0	0
T5	7563	2	0	0
T6	59776	40	0	0
T7	30512	53	0	0
T8	1465	4	0	0
T9	2650	2	0	0
T10	1969	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	44209	0	0
T1	15511	2	0	0
T2	52945	41	0	0
T3	1527	4	0	0
T4	14540	48	0	0
T5	7563	3	0	0
T6	59776	42	0	0
T7	30512	54	0	0
T8	1465	5	0	0
T9	2650	3	0	0
T10	1969	3	0	0