Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25876648	5671	0	0
EscTimeoutStoppedByClReset_A	25876044	3670387	0	0
EscTimeoutTriggersReset_A	4983969	297	0	0
RomAllowActiveState_A	25876044	62883	0	0
RomAllowCheckGoodState_A	25876044	62933	0	0
RomBlockActiveState_A	25876044	30458	0	0
RomBlockCheckGoodState_A	25876044	440110	0	0
RomIntgChkDisFalse_A	25876044	25155462	0	0
RomIntgChkDisTrue_A	25876044	178878	0	0
RstreqChkEsctimeout_A	25876044	4477	0	0
RstreqChkFsmterm_A	25876044	140	0	0
RstreqChkGlbesc_A	25876044	4477	0	0
RstreqChkMainpd_A	25876044	1054656	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876648	5671	0	0
T1	15512	257	0	0
T2	52945	0	0	0
T3	1527	0	0	0
T4	14541	0	0	0
T5	7563	0	0	0
T6	59776	0	0	0
T7	30512	0	0	0
T8	1466	0	0	0
T9	2651	0	0	0
T10	1970	0	0	0
T11	0	55	0	0
T12	0	6	0	0
T153	0	163	0	0
T167	0	26	0	0
T168	0	30	0	0
T169	0	145	0	0
T170	0	145	0	0
T171	0	19	0	0
T172	0	264	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	3670387	0	0
T1	15511	12	0	0
T2	52945	10805	0	0
T3	1527	41	0	0
T4	14540	1533	0	0
T5	7563	1073	0	0
T6	59776	10597	0	0
T7	30512	4472	0	0
T8	1465	130	0	0
T9	2650	12	0	0
T10	1969	182	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4983969	297	0	0
T1	208	3	0	0
T2	5494	0	0	0
T3	238	0	0	0
T4	5151	0	0	0
T5	715	0	0	0
T6	5822	0	0	0
T7	5896	0	0	0
T8	444	0	0	0
T9	229	0	0	0
T10	705	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T153	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	62883	0	0
T1	15511	2	0	0
T2	52945	80	0	0
T3	1527	4	0	0
T4	14540	65	0	0
T5	7563	8	0	0
T6	59776	82	0	0
T7	30512	89	0	0
T8	1465	5	0	0
T9	2650	3	0	0
T10	1969	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	62933	0	0
T1	15511	2	0	0
T2	52945	80	0	0
T3	1527	4	0	0
T4	14540	65	0	0
T5	7563	8	0	0
T6	59776	82	0	0
T7	30512	89	0	0
T8	1465	5	0	0
T9	2650	3	0	0
T10	1969	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	30458	0	0
T13	2270	0	0	0
T14	3351	0	0	0
T25	5843	1148	0	0
T38	29390	0	0	0
T39	58113	0	0	0
T43	0	232	0	0
T44	1599	0	0	0
T45	2114	0	0	0
T46	1573	0	0	0
T50	0	368	0	0
T81	1679	0	0	0
T82	1257	0	0	0
T87	0	11	0	0
T104	0	601	0	0
T159	0	6	0	0
T175	0	4	0	0
T176	0	464	0	0
T177	0	1015	0	0
T178	0	1352	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	440110	0	0
T2	52945	4112	0	0
T3	1527	0	0	0
T4	14540	0	0	0
T5	7563	0	0	0
T6	59776	4098	0	0
T7	30512	2287	0	0
T8	1465	0	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T24	0	4086	0	0
T25	0	743	0	0
T38	0	138	0	0
T39	0	1124	0	0
T40	7069	0	0	0
T43	0	67	0	0
T50	0	157	0	0
T179	0	411	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	25155462	0	0
T1	15511	15447	0	0
T2	52945	51875	0	0
T3	1527	1445	0	0
T4	14540	13969	0	0
T5	7563	7490	0	0
T6	59776	59614	0	0
T7	30512	30357	0	0
T8	1465	1415	0	0
T9	2650	2586	0	0
T10	1969	1907	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	178878	0	0
T2	52945	997	0	0
T3	1527	0	0	0
T4	14540	0	0	0
T5	7563	0	0	0
T6	59776	0	0	0
T7	30512	0	0	0
T8	1465	0	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T24	0	1566	0	0
T25	0	2773	0	0
T40	7069	0	0	0
T43	0	71	0	0
T50	0	876	0	0
T157	0	102	0	0
T176	0	983	0	0
T177	0	2141	0	0
T180	0	1036	0	0
T181	0	2390	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	4477	0	0
T1	15511	1	0	0
T2	52945	0	0	0
T3	1527	2	0	0
T4	14540	6	0	0
T5	7563	0	0	0
T6	59776	0	0	0
T7	30512	0	0	0
T8	1465	2	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T25	0	2	0	0
T37	0	6	0	0
T38	0	28	0	0
T39	0	14	0	0
T41	0	1	0	0
T42	0	8	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	140	0	0
T18	23830	20	0	0
T19	0	20	0	0
T20	0	40	0	0
T26	0	40	0	0
T27	0	20	0	0
T28	9239	0	0	0
T29	1748	0	0	0
T30	1083	0	0	0
T31	2528	0	0	0
T32	1048	0	0	0
T33	15132	0	0	0
T34	2409	0	0	0
T35	2558	0	0	0
T36	17714	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	4477	0	0
T1	15511	1	0	0
T2	52945	0	0	0
T3	1527	2	0	0
T4	14540	6	0	0
T5	7563	0	0	0
T6	59776	0	0	0
T7	30512	0	0	0
T8	1465	2	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T25	0	2	0	0
T37	0	6	0	0
T38	0	28	0	0
T39	0	14	0	0
T41	0	1	0	0
T42	0	8	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25876044	1054656	0	0
T2	52945	4342	0	0
T3	1527	0	0	0
T4	14540	135	0	0
T5	7563	0	0	0
T6	59776	4765	0	0
T7	30512	4466	0	0
T8	1465	76	0	0
T9	2650	0	0	0
T10	1969	0	0	0
T24	0	6186	0	0
T25	0	495	0	0
T37	0	151	0	0
T38	0	879	0	0
T39	0	1751	0	0
T40	7069	0	0	0