Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199129

1

T1

31

T2

135

T3

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	379165	1			T1	53		T2	246		T3	83
values[0x0]	173403	1			T1	20		T2	18		T3	58
values[0x1]	174245	1			T1	34		T2	15		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	417424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

309389

1

T1

50

T2

173

T3

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3373	1			T6	1		T37	1		T12	9
valid_sources[0x01]	2413	1			T1	1		T2	1		T6	4
valid_sources[0x02]	3738	1			T2	4		T6	6		T10	1
valid_sources[0x03]	2276	1			T6	5		T37	3		T39	1
valid_sources[0x04]	2154	1			T2	1		T6	4		T37	1
valid_sources[0x05]	2078	1			T2	2		T6	1		T37	1
valid_sources[0x06]	2783	1			T4	3		T6	3		T21	1
valid_sources[0x07]	4024	1			T6	2		T76	2		T12	13
valid_sources[0x08]	2466	1			T2	3		T4	2		T6	4
valid_sources[0x09]	2671	1			T1	1		T2	1		T6	1
valid_sources[0x0a]	2207	1			T2	1		T4	1		T39	2
valid_sources[0x0b]	3436	1			T4	2		T6	4		T37	3
valid_sources[0x0c]	1907	1			T2	1		T6	5		T37	2
valid_sources[0x0d]	2157	1			T6	3		T21	1		T37	3
valid_sources[0x0e]	2535	1			T2	1		T6	2		T10	5
valid_sources[0x0f]	2298	1			T2	2		T6	7		T37	5
valid_sources[0x10]	2739	1			T2	1		T4	2		T6	4
valid_sources[0x11]	3092	1			T1	1		T2	1		T6	2
valid_sources[0x12]	2153	1			T2	2		T5	1		T6	2
valid_sources[0x13]	4640	1			T1	1		T2	1		T4	1
valid_sources[0x14]	4482	1			T2	3		T6	6		T37	5
valid_sources[0x15]	2511	1			T6	4		T10	16		T39	2
valid_sources[0x16]	2110	1			T2	3		T6	2		T10	1
valid_sources[0x17]	3295	1			T6	2		T37	4		T40	4
valid_sources[0x18]	2254	1			T6	7		T37	2		T12	15
valid_sources[0x19]	3174	1			T2	2		T4	2		T6	3
valid_sources[0x1a]	2653	1			T6	3		T37	2		T39	1
valid_sources[0x1b]	2457	1			T2	3		T6	2		T37	2
valid_sources[0x1c]	2272	1			T2	1		T6	3		T21	1
valid_sources[0x1d]	2813	1			T2	1		T6	2		T10	2
valid_sources[0x1e]	2126	1			T1	1		T6	4		T10	1
valid_sources[0x1f]	3231	1			T1	2		T2	1		T4	1
valid_sources[0x20]	2139	1			T1	1		T2	2		T6	3
valid_sources[0x21]	2381	1			T2	2		T6	4		T10	3
valid_sources[0x22]	6598	1			T1	1		T2	3		T6	4
valid_sources[0x23]	2155	1			T2	1		T4	1		T6	3
valid_sources[0x24]	2233	1			T2	1		T4	1		T6	2
valid_sources[0x25]	2549	1			T1	1		T2	1		T6	1
valid_sources[0x26]	2007	1			T1	2		T2	4		T6	7
valid_sources[0x27]	2197	1			T4	1		T6	1		T21	1
valid_sources[0x28]	2355	1			T1	1		T6	3		T10	4
valid_sources[0x29]	3340	1			T2	3		T6	2		T37	2
valid_sources[0x2a]	2252	1			T2	1		T37	5		T40	3
valid_sources[0x2b]	2199	1			T1	1		T2	1		T12	20
valid_sources[0x2c]	3412	1			T2	1		T6	3		T37	3
valid_sources[0x2d]	2231	1			T2	1		T6	7		T21	2
valid_sources[0x2e]	2155	1			T2	3		T6	1		T37	2
valid_sources[0x2f]	3074	1			T1	1		T6	4		T12	12
valid_sources[0x30]	2629	1			T1	1		T6	1		T10	1
valid_sources[0x31]	5426	1			T2	1		T4	1		T6	1
valid_sources[0x32]	2646	1			T2	2		T37	3		T39	19
valid_sources[0x33]	3837	1			T1	1		T10	2		T21	1
valid_sources[0x34]	2847	1			T1	2		T2	1		T6	4
valid_sources[0x35]	3825	1			T1	1		T2	1		T6	3
valid_sources[0x36]	2159	1			T2	1		T6	1		T37	3
valid_sources[0x37]	5160	1			T1	1		T6	1		T10	14
valid_sources[0x38]	4213	1			T2	1		T6	6		T37	5
valid_sources[0x39]	2615	1			T2	1		T6	2		T76	1
valid_sources[0x3a]	2628	1			T1	1		T2	2		T6	6
valid_sources[0x3b]	2261	1			T1	3		T2	1		T6	8
valid_sources[0x3c]	2773	1			T6	1		T37	1		T40	4
valid_sources[0x3d]	2381	1			T2	1		T6	7		T76	7
valid_sources[0x3e]	2085	1			T2	1		T6	4		T37	1
valid_sources[0x3f]	2954	1			T1	1		T2	1		T6	2
valid_sources[0x40]	4074	1			T1	1		T2	4		T6	2
valid_sources[0x41]	2930	1			T1	1		T2	3		T4	1
valid_sources[0x42]	3286	1			T1	2		T2	1		T6	3
valid_sources[0x43]	2355	1			T1	1		T2	3		T6	2
valid_sources[0x44]	2725	1			T1	1		T2	2		T6	7
valid_sources[0x45]	2120	1			T2	2		T4	1		T6	5
valid_sources[0x46]	2514	1			T2	1		T6	1		T37	2
valid_sources[0x47]	2909	1			T2	3		T6	3		T76	1
valid_sources[0x48]	2489	1			T6	7		T10	1		T37	3
valid_sources[0x49]	2029	1			T2	1		T4	1		T6	5
valid_sources[0x4a]	1998	1			T2	1		T6	4		T37	2
valid_sources[0x4b]	2146	1			T6	5		T37	5		T12	22
valid_sources[0x4c]	2289	1			T6	2		T37	4		T39	12
valid_sources[0x4d]	2158	1			T1	2		T2	1		T6	1
valid_sources[0x4e]	5046	1			T1	1		T2	1		T6	3
valid_sources[0x4f]	2396	1			T6	2		T37	2		T39	5
valid_sources[0x50]	2069	1			T6	3		T10	1		T21	1
valid_sources[0x51]	2046	1			T2	2		T4	1		T6	2
valid_sources[0x52]	2254	1			T2	1		T6	3		T37	4
valid_sources[0x53]	2024	1			T6	2		T37	2		T12	13
valid_sources[0x54]	2145	1			T2	1		T4	2		T6	3
valid_sources[0x55]	2035	1			T6	5		T37	3		T39	5
valid_sources[0x56]	2233	1			T2	4		T4	2		T6	4
valid_sources[0x57]	2435	1			T2	3		T6	2		T10	1
valid_sources[0x58]	2163	1			T1	1		T6	7		T76	2
valid_sources[0x59]	2106	1			T2	1		T4	1		T10	3
valid_sources[0x5a]	2551	1			T6	3		T37	3		T12	17
valid_sources[0x5b]	2648	1			T2	1		T4	1		T37	6
valid_sources[0x5c]	2400	1			T1	1		T6	4		T21	2
valid_sources[0x5d]	2633	1			T1	1		T2	1		T6	1
valid_sources[0x5e]	5138	1			T2	2		T6	3		T39	7
valid_sources[0x5f]	4282	1			T10	7		T21	1		T76	6
valid_sources[0x60]	2171	1			T2	3		T6	2		T10	2
valid_sources[0x61]	2532	1			T1	2		T2	1		T6	2
valid_sources[0x62]	2207	1			T2	1		T6	4		T37	4
valid_sources[0x63]	2623	1			T2	1		T6	3		T37	1
valid_sources[0x64]	3071	1			T76	6		T37	3		T39	9
valid_sources[0x65]	2498	1			T1	1		T2	1		T6	6
valid_sources[0x66]	2531	1			T2	2		T6	5		T37	4
valid_sources[0x67]	3238	1			T2	2		T6	3		T21	1
valid_sources[0x68]	2291	1			T1	1		T2	2		T6	2
valid_sources[0x69]	2208	1			T2	4		T6	2		T76	4
valid_sources[0x6a]	2232	1			T2	1		T6	2		T37	1
valid_sources[0x6b]	1917	1			T4	1		T6	2		T21	1
valid_sources[0x6c]	2534	1			T1	1		T2	2		T6	4
valid_sources[0x6d]	4512	1			T6	6		T37	2		T12	25
valid_sources[0x6e]	2213	1			T6	3		T76	1		T37	5
valid_sources[0x6f]	3062	1			T6	6		T76	20		T37	2
valid_sources[0x70]	2813	1			T1	1		T6	5		T10	1
valid_sources[0x71]	2299	1			T2	2		T6	5		T76	1
valid_sources[0x72]	2157	1			T2	2		T6	5		T76	14
valid_sources[0x73]	2361	1			T1	2		T2	1		T6	4
valid_sources[0x74]	2486	1			T1	1		T6	4		T76	1
valid_sources[0x75]	4167	1			T6	8		T40	1		T12	19
valid_sources[0x76]	2469	1			T2	1		T6	6		T10	1
valid_sources[0x77]	3652	1			T6	4		T10	1		T37	1
valid_sources[0x78]	2082	1			T6	4		T37	1		T39	1
valid_sources[0x79]	1948	1			T1	2		T6	2		T37	1
valid_sources[0x7a]	3052	1			T1	2		T6	4		T37	1
valid_sources[0x7b]	3537	1			T1	1		T2	2		T4	1
valid_sources[0x7c]	2078	1			T1	1		T6	4		T37	3
valid_sources[0x7d]	3953	1			T2	2		T6	5		T37	3
valid_sources[0x7e]	2530	1			T2	1		T6	4		T10	1
valid_sources[0x7f]	3454	1			T1	1		T2	2		T6	3
valid_sources[0x80]	3650	1			T6	2		T37	5		T12	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

100592

1

T1

16

T2

126

T3

23

values[0x0]

all_enables

biggest_size

64025

1

T1

11

T2

8

T3

13

values[0x1]

all_enables

biggest_size

34512

1

T1

4

T2

1

T3

8