SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35310 | 1 | T6 | 312 | T39 | 399 | T183 | 398 | ||||
others[1] | 35048 | 1 | T6 | 316 | T39 | 397 | T183 | 379 | ||||
others[2] | 35245 | 1 | T6 | 283 | T39 | 391 | T183 | 397 | ||||
others[3] | 58012 | 1 | T6 | 491 | T39 | 683 | T183 | 686 | ||||
false | 19336 | 1 | T4 | 4 | T6 | 50 | T7 | 22 | ||||
true | 29672 | 1 | T1 | 1 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35032 | 1 | T6 | 284 | T39 | 397 | T183 | 418 | ||||
others[1] | 34846 | 1 | T4 | 1 | T6 | 310 | T39 | 399 | ||||
others[2] | 35156 | 1 | T6 | 308 | T39 | 407 | T183 | 393 | ||||
others[3] | 58469 | 1 | T6 | 488 | T39 | 659 | T183 | 653 | ||||
false | 12271 | 1 | T4 | 2 | T6 | 50 | T7 | 11 | ||||
true | 22663 | 1 | T1 | 1 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 721 | 1 | T9 | 2 | T76 | 7 | T40 | 1 | ||||
others[1] | 685 | 1 | T2 | 2 | T9 | 1 | T76 | 4 | ||||
others[2] | 746 | 1 | T2 | 1 | T4 | 1 | T9 | 1 | ||||
others[3] | 1185 | 1 | T9 | 3 | T76 | 8 | T24 | 1 | ||||
false | 14420 | 1 | T1 | 1 | T2 | 23 | T3 | 1 | ||||
true | 4364 | 1 | T2 | 7 | T4 | 3 | T9 | 11 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |