Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25032198	14225	0	0
intr_enable_rd_A	25032198	46406	0	0
reset_en_rd_A	25032198	1162	0	0
reset_en_regwen_rd_A	25032198	1158	0	0
wake_info_capture_dis_rd_A	25032198	1095	0	0
wakeup_en_rd_A	25032198	1755	0	0
wakeup_en_regwen_rd_A	25032198	1159	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	14225	0	0
T12	106507	5	0	0
T13	2250	0	0	0
T16	1363	0	0	0
T22	0	35	0	0
T23	0	3	0	0
T41	4617	0	0	0
T42	4488	0	0	0
T43	2635	0	0	0
T44	4641	0	0	0
T46	1858	0	0	0
T49	0	116	0	0
T52	0	25	0	0
T53	0	26	0	0
T89	0	15	0	0
T91	2483	0	0	0
T127	0	44	0	0
T128	0	7	0	0
T129	0	83	0	0
T130	6119	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	46406	0	0
T4	2086	12	0	0
T5	15205	0	0	0
T6	28389	0	0	0
T7	10690	15	0	0
T8	15049	0	0	0
T9	20064	0	0	0
T10	6302	55	0	0
T13	0	12	0	0
T21	3032	0	0	0
T22	0	1716	0	0
T24	0	19	0	0
T37	10158	0	0	0
T76	7253	124	0	0
T82	0	127	0	0
T83	0	37	0	0
T131	0	3	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	1162	0	0
T55	0	99	0	0
T78	100833	0	0	0
T79	246050	0	0	0
T117	0	7	0	0
T118	0	31	0	0
T132	581577	17	0	0
T133	0	2	0	0
T134	0	4	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	3273	0	0	0
T140	2929	0	0	0
T141	1513	0	0	0
T142	2317	0	0	0
T143	1499	0	0	0
T144	6763	0	0	0
T145	10104	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	1158	0	0
T22	639559	7	0	0
T55	0	83	0	0
T68	0	7	0	0
T80	913	0	0	0
T81	7569	0	0	0
T82	4376	0	0	0
T83	21681	0	0	0
T84	1449	0	0	0
T85	18651	0	0	0
T86	1130	0	0	0
T87	12004	0	0	0
T88	1182	0	0	0
T89	0	1	0	0
T117	0	14	0	0
T132	0	7	0	0
T133	0	4	0	0
T134	0	7	0	0
T135	0	11	0	0
T146	0	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	1095	0	0
T55	0	78	0	0
T68	0	4	0	0
T117	0	30	0	0
T132	0	11	0	0
T133	0	6	0	0
T134	0	7	0	0
T135	0	3	0	0
T136	0	4	0	0
T146	0	1	0	0
T147	129113	5	0	0
T148	3490	0	0	0
T149	1269	0	0	0
T150	2108	0	0	0
T151	7055	0	0	0
T152	13256	0	0	0
T153	47894	0	0	0
T154	18247	0	0	0
T155	9420	0	0	0
T156	802	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	1755	0	0
T54	0	4	0	0
T55	0	318	0	0
T59	14589	0	0	0
T68	0	16	0	0
T89	479210	3	0	0
T97	58370	0	0	0
T126	63909	0	0	0
T132	0	16	0	0
T133	0	6	0	0
T134	0	4	0	0
T135	0	12	0	0
T146	0	5	0	0
T157	0	1	0	0
T158	15667	0	0	0
T159	27115	0	0	0
T160	1658	0	0	0
T161	15024	0	0	0
T162	10989	0	0	0
T163	5840	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25032198	1159	0	0
T22	639559	8	0	0
T54	0	8	0	0
T55	0	64	0	0
T68	0	3	0	0
T80	913	0	0	0
T81	7569	0	0	0
T82	4376	0	0	0
T83	21681	0	0	0
T84	1449	0	0	0
T85	18651	0	0	0
T86	1130	0	0	0
T87	12004	0	0	0
T88	1182	0	0	0
T89	0	8	0	0
T117	0	23	0	0
T132	0	17	0	0
T133	0	1	0	0
T135	0	1	0	0
T146	0	8	0	0