Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73217673	150534	0	0
StatusRise_A	73217673	168169	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73217673	150534	0	0
T1	11310	20	0	0
T2	22449	54	0	0
T3	38898	40	0	0
T4	6258	15	0	0
T5	45615	3	0	0
T6	85167	227	0	0
T7	32070	40	0	0
T8	45147	3	0	0
T9	60192	199	0	0
T10	18906	41	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73217673	168169	0	0
T1	11310	22	0	0
T2	22449	60	0	0
T3	38898	43	0	0
T4	6258	21	0	0
T5	45615	6	0	0
T6	85167	232	0	0
T7	32070	45	0	0
T8	45147	6	0	0
T9	60192	231	0	0
T10	18906	43	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24405891	55775	0	0
StatusRise_A	24405891	62142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	55775	0	0
T1	3770	7	0	0
T2	7483	18	0	0
T3	12966	15	0	0
T4	2086	5	0	0
T5	15205	1	0	0
T6	28389	88	0	0
T7	10690	18	0	0
T8	15049	1	0	0
T9	20064	73	0	0
T10	6302	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	62142	0	0
T1	3770	8	0	0
T2	7483	20	0	0
T3	12966	16	0	0
T4	2086	7	0	0
T5	15205	2	0	0
T6	28389	90	0	0
T7	10690	20	0	0
T8	15049	2	0	0
T9	20064	84	0	0
T10	6302	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24405891	55775	0	0
StatusRise_A	24405891	62142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	55775	0	0
T1	3770	7	0	0
T2	7483	18	0	0
T3	12966	15	0	0
T4	2086	5	0	0
T5	15205	1	0	0
T6	28389	88	0	0
T7	10690	18	0	0
T8	15049	1	0	0
T9	20064	73	0	0
T10	6302	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	62142	0	0
T1	3770	8	0	0
T2	7483	20	0	0
T3	12966	16	0	0
T4	2086	7	0	0
T5	15205	2	0	0
T6	28389	90	0	0
T7	10690	20	0	0
T8	15049	2	0	0
T9	20064	84	0	0
T10	6302	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24405891	38984	0	0
StatusRise_A	24405891	43885	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	38984	0	0
T1	3770	6	0	0
T2	7483	18	0	0
T3	12966	10	0	0
T4	2086	5	0	0
T5	15205	1	0	0
T6	28389	51	0	0
T7	10690	4	0	0
T8	15049	1	0	0
T9	20064	53	0	0
T10	6302	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	43885	0	0
T1	3770	6	0	0
T2	7483	20	0	0
T3	12966	11	0	0
T4	2086	7	0	0
T5	15205	2	0	0
T6	28389	52	0	0
T7	10690	5	0	0
T8	15049	2	0	0
T9	20064	63	0	0
T10	6302	9	0	0