Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24406487	5361	0	0
EscTimeoutStoppedByClReset_A	24405891	3317238	0	0
EscTimeoutTriggersReset_A	5132820	329	0	0
RomAllowActiveState_A	24405891	61765	0	0
RomAllowCheckGoodState_A	24405891	61818	0	0
RomBlockActiveState_A	24405891	28205	0	0
RomBlockCheckGoodState_A	24405891	440456	0	0
RomIntgChkDisFalse_A	24405891	23715652	0	0
RomIntgChkDisTrue_A	24405891	143113	0	0
RstreqChkEsctimeout_A	24405891	4736	0	0
RstreqChkFsmterm_A	24405891	180	0	0
RstreqChkGlbesc_A	24405891	4736	0	0
RstreqChkMainpd_A	24405891	1014541	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24406487	5361	0	0
T5	15205	74	0	0
T6	28389	0	0	0
T7	10691	0	0	0
T8	15050	27	0	0
T9	20065	0	0	0
T10	6302	0	0	0
T11	0	130	0	0
T21	3032	0	0	0
T37	10158	0	0	0
T38	6755	0	0	0
T76	7254	0	0	0
T165	0	52	0	0
T166	0	56	0	0
T167	0	34	0	0
T168	0	96	0	0
T169	0	19	0	0
T170	0	186	0	0
T171	0	32	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	3317238	0	0
T1	3770	908	0	0
T2	7483	286	0	0
T3	12966	1918	0	0
T4	2086	110	0	0
T5	15205	11	0	0
T6	28389	5638	0	0
T7	10690	1727	0	0
T8	15049	13	0	0
T9	20064	3201	0	0
T10	6302	934	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5132820	329	0	0
T5	353	2	0	0
T6	6083	0	0	0
T7	1421	0	0	0
T8	1008	2	0	0
T9	6105	0	0	0
T10	2617	0	0	0
T11	0	2	0	0
T21	292	0	0	0
T37	6770	0	0	0
T38	1325	0	0	0
T76	525	0	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0
T171	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	61765	0	0
T1	3770	8	0	0
T2	7483	13	0	0
T3	12966	16	0	0
T4	2086	7	0	0
T5	15205	2	0	0
T6	28389	90	0	0
T7	10690	20	0	0
T8	15049	2	0	0
T9	20064	84	0	0
T10	6302	17	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	61818	0	0
T1	3770	8	0	0
T2	7483	14	0	0
T3	12966	16	0	0
T4	2086	7	0	0
T5	15205	2	0	0
T6	28389	90	0	0
T7	10690	20	0	0
T8	15049	2	0	0
T9	20064	84	0	0
T10	6302	17	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	28205	0	0
T4	2086	304	0	0
T5	15205	0	0	0
T6	28389	0	0	0
T7	10690	0	0	0
T8	15049	0	0	0
T9	20064	0	0	0
T10	6302	0	0	0
T21	3032	0	0	0
T24	0	329	0	0
T29	0	600	0	0
T32	0	14	0	0
T37	10158	0	0	0
T48	0	15	0	0
T76	7253	0	0	0
T159	0	19	0	0
T160	0	217	0	0
T172	0	226	0	0
T173	0	121	0	0
T174	0	12	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	440456	0	0
T4	2086	99	0	0
T5	15205	0	0	0
T6	28389	2185	0	0
T7	10690	253	0	0
T8	15049	0	0	0
T9	20064	529	0	0
T10	6302	0	0	0
T12	0	391	0	0
T21	3032	0	0	0
T24	0	71	0	0
T37	10158	344	0	0
T38	0	227	0	0
T39	0	1451	0	0
T45	0	183	0	0
T76	7253	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	23715652	0	0
T1	3770	3714	0	0
T2	7483	6522	0	0
T3	12966	12907	0	0
T4	2086	1119	0	0
T5	15205	15111	0	0
T6	28389	27070	0	0
T7	10690	10499	0	0
T8	15049	14976	0	0
T9	20064	19244	0	0
T10	6302	6235	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	143113	0	0
T4	2086	823	0	0
T5	15205	0	0	0
T6	28389	1169	0	0
T7	10690	0	0	0
T8	15049	0	0	0
T9	20064	0	0	0
T10	6302	0	0	0
T21	3032	0	0	0
T24	0	301	0	0
T25	0	622	0	0
T29	0	318	0	0
T32	0	225	0	0
T37	10158	0	0	0
T76	7253	0	0	0
T173	0	472	0	0
T174	0	238	0	0
T175	0	829	0	0
T176	0	1103	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	4736	0	0
T2	7483	8	0	0
T3	12966	0	0	0
T4	2086	4	0	0
T5	15205	1	0	0
T6	28389	0	0	0
T7	10690	0	0	0
T8	15049	1	0	0
T9	20064	14	0	0
T10	6302	0	0	0
T12	0	48	0	0
T21	3032	0	0	0
T24	0	2	0	0
T40	0	9	0	0
T41	0	6	0	0
T43	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	180	0	0
T18	44655	40	0	0
T19	0	40	0	0
T20	0	40	0	0
T26	0	20	0	0
T27	0	40	0	0
T28	6497	0	0	0
T29	5159	0	0	0
T30	1852	0	0	0
T31	1735	0	0	0
T32	24328	0	0	0
T33	1829	0	0	0
T34	60575	0	0	0
T35	1481	0	0	0
T36	1813	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	4736	0	0
T2	7483	8	0	0
T3	12966	0	0	0
T4	2086	4	0	0
T5	15205	1	0	0
T6	28389	0	0	0
T7	10690	0	0	0
T8	15049	1	0	0
T9	20064	14	0	0
T10	6302	0	0	0
T12	0	48	0	0
T21	3032	0	0	0
T24	0	2	0	0
T40	0	9	0	0
T41	0	6	0	0
T43	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24405891	1014541	0	0
T2	7483	134	0	0
T3	12966	0	0	0
T4	2086	56	0	0
T5	15205	0	0	0
T6	28389	2415	0	0
T7	10690	813	0	0
T8	15049	0	0	0
T9	20064	1397	0	0
T10	6302	0	0	0
T15	0	21	0	0
T21	3032	0	0	0
T24	0	66	0	0
T37	0	169	0	0
T38	0	831	0	0
T39	0	1416	0	0