Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	518488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

191645

1

T1

12

T2

6

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	364513	1			T1	28		T2	6		T3	17
values[0x0]	172516	1			T1	5		T2	11		T3	6
values[0x1]	173104	1			T1	9		T2	5		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	410367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

299766

1

T1

19

T2

8

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3193	1			T5	1		T9	4		T27	1
valid_sources[0x01]	3137	1			T9	3		T16	1		T15	6
valid_sources[0x02]	2170	1			T1	1		T6	1		T41	12
valid_sources[0x03]	3258	1			T4	2		T9	3		T47	1
valid_sources[0x04]	2036	1			T4	1		T5	2		T9	4
valid_sources[0x05]	2290	1			T16	3		T20	1		T47	1
valid_sources[0x06]	2262	1			T5	1		T9	5		T16	1
valid_sources[0x07]	2378	1			T9	3		T27	2		T39	2
valid_sources[0x08]	3046	1			T9	6		T46	1		T47	1
valid_sources[0x09]	3850	1			T4	1		T9	2		T27	1
valid_sources[0x0a]	3745	1			T4	1		T9	2		T46	2
valid_sources[0x0b]	2358	1			T9	3		T29	1		T41	2
valid_sources[0x0c]	2496	1			T9	4		T16	2		T14	2
valid_sources[0x0d]	2460	1			T9	8		T16	1		T27	1
valid_sources[0x0e]	3332	1			T9	3		T16	3		T27	1
valid_sources[0x0f]	2206	1			T1	1		T4	1		T9	3
valid_sources[0x10]	3935	1			T4	1		T9	2		T10	1
valid_sources[0x11]	3957	1			T6	1		T9	5		T16	1
valid_sources[0x12]	2326	1			T5	1		T6	1		T9	4
valid_sources[0x13]	1950	1			T4	1		T9	1		T16	3
valid_sources[0x14]	1961	1			T6	1		T9	1		T16	3
valid_sources[0x15]	4762	1			T4	2		T9	2		T16	3
valid_sources[0x16]	2157	1			T1	1		T4	2		T9	3
valid_sources[0x17]	2614	1			T3	1		T4	2		T9	1
valid_sources[0x18]	3891	1			T4	2		T5	2		T9	7
valid_sources[0x19]	2264	1			T4	1		T9	2		T27	1
valid_sources[0x1a]	2324	1			T4	1		T9	2		T16	1
valid_sources[0x1b]	2578	1			T1	1		T6	1		T9	4
valid_sources[0x1c]	2097	1			T4	1		T9	3		T16	1
valid_sources[0x1d]	4184	1			T9	9		T16	1		T27	1
valid_sources[0x1e]	2180	1			T9	2		T16	2		T27	2
valid_sources[0x1f]	4238	1			T4	1		T9	1		T16	3
valid_sources[0x20]	2120	1			T9	4		T27	3		T14	1
valid_sources[0x21]	2350	1			T4	1		T9	3		T16	2
valid_sources[0x22]	2993	1			T5	1		T9	4		T27	2
valid_sources[0x23]	2383	1			T16	2		T41	6		T178	1
valid_sources[0x24]	3782	1			T1	1		T9	4		T27	4
valid_sources[0x25]	3077	1			T1	1		T9	4		T16	4
valid_sources[0x26]	2720	1			T9	6		T17	1		T46	1
valid_sources[0x27]	1917	1			T4	2		T9	1		T16	2
valid_sources[0x28]	3226	1			T4	2		T9	7		T16	6
valid_sources[0x29]	3022	1			T9	4		T16	2		T27	2
valid_sources[0x2a]	2122	1			T1	2		T3	1		T9	4
valid_sources[0x2b]	2815	1			T16	4		T27	2		T20	2
valid_sources[0x2c]	3259	1			T1	1		T4	2		T9	7
valid_sources[0x2d]	2223	1			T4	1		T16	4		T14	2
valid_sources[0x2e]	2035	1			T3	1		T4	2		T9	4
valid_sources[0x2f]	2213	1			T9	1		T16	5		T20	2
valid_sources[0x30]	2204	1			T4	1		T9	2		T16	1
valid_sources[0x31]	2174	1			T4	1		T9	7		T16	2
valid_sources[0x32]	2039	1			T3	1		T9	1		T16	4
valid_sources[0x33]	4001	1			T4	3		T9	3		T16	2
valid_sources[0x34]	2043	1			T4	3		T6	1		T9	6
valid_sources[0x35]	2432	1			T4	2		T5	1		T9	3
valid_sources[0x36]	3527	1			T4	1		T9	3		T16	2
valid_sources[0x37]	5688	1			T4	1		T9	4		T16	2
valid_sources[0x38]	2711	1			T3	1		T4	2		T9	2
valid_sources[0x39]	2019	1			T4	1		T9	6		T16	2
valid_sources[0x3a]	2110	1			T1	1		T9	4		T20	1
valid_sources[0x3b]	2189	1			T9	7		T47	3		T41	6
valid_sources[0x3c]	3491	1			T9	3		T20	2		T14	1
valid_sources[0x3d]	2350	1			T9	6		T16	11		T27	1
valid_sources[0x3e]	2368	1			T3	1		T9	5		T16	2
valid_sources[0x3f]	2441	1			T4	1		T9	2		T16	1
valid_sources[0x40]	2087	1			T9	5		T16	5		T178	2
valid_sources[0x41]	2588	1			T4	1		T9	3		T16	2
valid_sources[0x42]	3192	1			T6	1		T9	8		T16	1
valid_sources[0x43]	3160	1			T4	2		T16	2		T27	1
valid_sources[0x44]	2764	1			T9	4		T16	11		T47	1
valid_sources[0x45]	2019	1			T4	1		T9	3		T16	1
valid_sources[0x46]	3166	1			T4	2		T9	6		T16	5
valid_sources[0x47]	3076	1			T1	1		T4	2		T9	5
valid_sources[0x48]	2005	1			T1	2		T3	1		T9	3
valid_sources[0x49]	2275	1			T1	1		T9	4		T16	2
valid_sources[0x4a]	2406	1			T9	3		T16	3		T46	1
valid_sources[0x4b]	3207	1			T4	1		T9	1		T16	1
valid_sources[0x4c]	3250	1			T3	1		T16	1		T27	1
valid_sources[0x4d]	2135	1			T1	1		T9	2		T85	4
valid_sources[0x4e]	2182	1			T9	3		T16	3		T14	1
valid_sources[0x4f]	2077	1			T9	7		T16	1		T27	3
valid_sources[0x50]	2365	1			T1	1		T4	1		T9	6
valid_sources[0x51]	3764	1			T9	3		T16	1		T20	1
valid_sources[0x52]	4544	1			T4	2		T9	4		T16	1
valid_sources[0x53]	2109	1			T9	4		T16	6		T47	1
valid_sources[0x54]	2655	1			T9	3		T27	1		T28	4
valid_sources[0x55]	1985	1			T4	2		T9	1		T16	2
valid_sources[0x56]	2114	1			T4	1		T5	4		T9	2
valid_sources[0x57]	3668	1			T4	1		T9	4		T16	2
valid_sources[0x58]	2076	1			T3	1		T9	7		T16	1
valid_sources[0x59]	2166	1			T5	2		T9	1		T47	2
valid_sources[0x5a]	2153	1			T9	2		T27	1		T20	1
valid_sources[0x5b]	1951	1			T4	1		T9	5		T27	2
valid_sources[0x5c]	2102	1			T9	2		T16	6		T24	59
valid_sources[0x5d]	2115	1			T1	2		T9	2		T46	2
valid_sources[0x5e]	3067	1			T1	1		T9	8		T16	3
valid_sources[0x5f]	3821	1			T4	1		T9	3		T27	1
valid_sources[0x60]	2137	1			T6	1		T9	8		T16	7
valid_sources[0x61]	3252	1			T1	1		T4	1		T8	1
valid_sources[0x62]	2038	1			T1	1		T9	4		T16	2
valid_sources[0x63]	2608	1			T9	4		T16	2		T17	1
valid_sources[0x64]	3084	1			T3	1		T4	3		T9	5
valid_sources[0x65]	2333	1			T4	1		T6	1		T9	6
valid_sources[0x66]	2206	1			T4	2		T9	2		T16	4
valid_sources[0x67]	2604	1			T4	1		T9	4		T16	3
valid_sources[0x68]	2399	1			T9	5		T16	2		T47	1
valid_sources[0x69]	2025	1			T1	1		T9	2		T16	3
valid_sources[0x6a]	4283	1			T4	1		T9	2		T17	1
valid_sources[0x6b]	2126	1			T4	1		T9	3		T16	2
valid_sources[0x6c]	3742	1			T1	1		T4	1		T9	4
valid_sources[0x6d]	2668	1			T4	2		T16	1		T17	1
valid_sources[0x6e]	2580	1			T4	2		T9	3		T16	3
valid_sources[0x6f]	9740	1			T9	3		T16	3		T12	1
valid_sources[0x70]	2541	1			T1	1		T9	6		T16	3
valid_sources[0x71]	5264	1			T9	2		T16	2		T27	1
valid_sources[0x72]	3667	1			T1	1		T4	2		T9	4
valid_sources[0x73]	2288	1			T3	1		T4	1		T9	5
valid_sources[0x74]	3299	1			T1	1		T6	1		T9	4
valid_sources[0x75]	2308	1			T4	3		T5	2		T9	1
valid_sources[0x76]	3077	1			T4	1		T9	4		T16	1
valid_sources[0x77]	2439	1			T4	2		T9	4		T16	1
valid_sources[0x78]	3428	1			T4	1		T9	3		T27	2
valid_sources[0x79]	2433	1			T4	3		T9	2		T16	3
valid_sources[0x7a]	2392	1			T4	1		T9	5		T14	1
valid_sources[0x7b]	1957	1			T3	1		T4	2		T9	1
valid_sources[0x7c]	2294	1			T4	3		T9	5		T16	3
valid_sources[0x7d]	3267	1			T4	1		T9	4		T16	1
valid_sources[0x7e]	2010	1			T1	1		T3	1		T4	1
valid_sources[0x7f]	2975	1			T1	1		T4	4		T9	4
valid_sources[0x80]	2351	1			T3	1		T9	5		T16	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93254

1

T1

9

T2

1

T3

7

values[0x0]

all_enables

biggest_size

64011

1

T1

1

T2

5

T3

1

values[0x1]

all_enables

biggest_size

34380

1

T1

2

T4

15

T5

5