SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35149 | 1 | T9 | 417 | T40 | 387 | T41 | 407 | ||||
others[1] | 34820 | 1 | T9 | 394 | T40 | 422 | T41 | 372 | ||||
others[2] | 35068 | 1 | T9 | 393 | T40 | 405 | T41 | 410 | ||||
others[3] | 58267 | 1 | T9 | 671 | T15 | 1 | T40 | 655 | ||||
false | 19720 | 1 | T9 | 50 | T20 | 14 | T15 | 3 | ||||
true | 29934 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35118 | 1 | T9 | 416 | T40 | 393 | T41 | 389 | ||||
others[1] | 34919 | 1 | T9 | 383 | T15 | 2 | T40 | 392 | ||||
others[2] | 35086 | 1 | T9 | 387 | T40 | 423 | T41 | 396 | ||||
others[3] | 58411 | 1 | T9 | 677 | T40 | 643 | T28 | 1 | ||||
false | 12460 | 1 | T9 | 50 | T20 | 7 | T15 | 3 | ||||
true | 22736 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 696 | 1 | T7 | 7 | T14 | 1 | T28 | 1 | ||||
others[1] | 749 | 1 | T7 | 8 | T14 | 1 | T29 | 1 | ||||
others[2] | 769 | 1 | T7 | 4 | T39 | 1 | T15 | 1 | ||||
others[3] | 1234 | 1 | T7 | 5 | T14 | 2 | T28 | 1 | ||||
false | 14180 | 1 | T1 | 1 | T2 | 5 | T3 | 1 | ||||
true | 4186 | 1 | T7 | 2 | T14 | 4 | T15 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |