Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25479683	13178	0	0
intr_enable_rd_A	25479683	42479	0	0
reset_en_rd_A	25479683	1114	0	0
reset_en_regwen_rd_A	25479683	873	0	0
wake_info_capture_dis_rd_A	25479683	851	0	0
wakeup_en_rd_A	25479683	1628	0	0
wakeup_en_regwen_rd_A	25479683	981	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	13178	0	0
T24	443230	17	0	0
T25	0	29	0	0
T26	0	27	0	0
T55	0	39	0	0
T88	0	3	0	0
T92	29156	0	0	0
T93	7708	0	0	0
T94	2324	0	0	0
T95	1116	0	0	0
T96	4973	0	0	0
T97	17281	0	0	0
T98	7676	0	0	0
T99	10696	0	0	0
T100	4670	0	0	0
T141	0	20	0	0
T142	0	7	0	0
T143	0	3	0	0
T144	0	1	0	0
T145	0	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	42479	0	0
T1	3969	6	0	0
T2	2692	0	0	0
T3	1129	0	0	0
T4	2405	0	0	0
T5	4716	29	0	0
T6	1345	0	0	0
T7	4997	105	0	0
T8	1275	0	0	0
T9	54442	0	0	0
T10	1362	0	0	0
T28	0	19	0	0
T49	0	8	0	0
T50	0	70	0	0
T66	0	50	0	0
T67	0	46	0	0
T84	0	18	0	0
T146	0	49	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	1114	0	0
T26	787928	8	0	0
T57	0	10	0	0
T59	0	48	0	0
T90	0	10	0	0
T103	26040	0	0	0
T104	2330	0	0	0
T105	8696	0	0	0
T106	23730	0	0	0
T107	1141	0	0	0
T108	4598	0	0	0
T109	948	0	0	0
T110	56599	0	0	0
T111	2858	0	0	0
T139	0	23	0	0
T141	0	2	0	0
T144	0	9	0	0
T147	0	4	0	0
T148	0	11	0	0
T149	0	10	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	873	0	0
T26	787928	10	0	0
T57	0	20	0	0
T59	0	45	0	0
T90	0	2	0	0
T103	26040	0	0	0
T104	2330	0	0	0
T105	8696	0	0	0
T106	23730	0	0	0
T107	1141	0	0	0
T108	4598	0	0	0
T109	948	0	0	0
T110	56599	0	0	0
T111	2858	0	0	0
T139	0	35	0	0
T141	0	6	0	0
T147	0	8	0	0
T148	0	15	0	0
T149	0	21	0	0
T150	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	851	0	0
T26	787928	9	0	0
T57	0	15	0	0
T59	0	54	0	0
T90	0	9	0	0
T103	26040	0	0	0
T104	2330	0	0	0
T105	8696	0	0	0
T106	23730	0	0	0
T107	1141	0	0	0
T108	4598	0	0	0
T109	948	0	0	0
T110	56599	0	0	0
T111	2858	0	0	0
T139	0	30	0	0
T141	0	6	0	0
T147	0	2	0	0
T148	0	5	0	0
T149	0	5	0	0
T150	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	1628	0	0
T26	787928	10	0	0
T57	0	9	0	0
T59	0	157	0	0
T90	0	12	0	0
T103	26040	0	0	0
T104	2330	0	0	0
T105	8696	0	0	0
T106	23730	0	0	0
T107	1141	0	0	0
T108	4598	0	0	0
T109	948	0	0	0
T110	56599	0	0	0
T111	2858	0	0	0
T139	0	30	0	0
T141	0	4	0	0
T144	0	8	0	0
T147	0	10	0	0
T148	0	19	0	0
T149	0	15	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25479683	981	0	0
T26	787928	5	0	0
T57	0	15	0	0
T59	0	28	0	0
T90	0	6	0	0
T103	26040	0	0	0
T104	2330	0	0	0
T105	8696	0	0	0
T106	23730	0	0	0
T107	1141	0	0	0
T108	4598	0	0	0
T109	948	0	0	0
T110	56599	0	0	0
T111	2858	0	0	0
T139	0	51	0	0
T141	0	10	0	0
T144	0	6	0	0
T147	0	8	0	0
T148	0	14	0	0
T149	0	10	0	0