Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	74794758	149751	0	0
StatusRise_A	74794758	167177	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74794758	149751	0	0
T1	11907	6	0	0
T2	8076	12	0	0
T3	3387	6	0	0
T4	7215	42	0	0
T5	14148	14	0	0
T6	4035	12	0	0
T7	14991	6	0	0
T8	3825	0	0	0
T9	163326	213	0	0
T10	4086	0	0	0
T11	0	3	0	0
T16	0	55	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74794758	167177	0	0
T1	11907	9	0	0
T2	8076	15	0	0
T3	3387	9	0	0
T4	7215	45	0	0
T5	14148	17	0	0
T6	4035	15	0	0
T7	14991	9	0	0
T8	3825	12	0	0
T9	163326	216	0	0
T10	4086	21	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24931586	55512	0	0
StatusRise_A	24931586	61818	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	55512	0	0
T1	3969	2	0	0
T2	2692	4	0	0
T3	1129	2	0	0
T4	2405	15	0	0
T5	4716	5	0	0
T6	1345	4	0	0
T7	4997	2	0	0
T8	1275	0	0	0
T9	54442	85	0	0
T10	1362	0	0	0
T11	0	1	0	0
T16	0	19	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	61818	0	0
T1	3969	3	0	0
T2	2692	5	0	0
T3	1129	3	0	0
T4	2405	16	0	0
T5	4716	6	0	0
T6	1345	5	0	0
T7	4997	3	0	0
T8	1275	4	0	0
T9	54442	86	0	0
T10	1362	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24931586	55512	0	0
StatusRise_A	24931586	61824	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	55512	0	0
T1	3969	2	0	0
T2	2692	4	0	0
T3	1129	2	0	0
T4	2405	15	0	0
T5	4716	5	0	0
T6	1345	4	0	0
T7	4997	2	0	0
T8	1275	0	0	0
T9	54442	85	0	0
T10	1362	0	0	0
T11	0	1	0	0
T16	0	19	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	61824	0	0
T1	3969	3	0	0
T2	2692	5	0	0
T3	1129	3	0	0
T4	2405	16	0	0
T5	4716	6	0	0
T6	1345	5	0	0
T7	4997	3	0	0
T8	1275	4	0	0
T9	54442	86	0	0
T10	1362	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24931586	38727	0	0
StatusRise_A	24931586	43535	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	38727	0	0
T1	3969	2	0	0
T2	2692	4	0	0
T3	1129	2	0	0
T4	2405	12	0	0
T5	4716	4	0	0
T6	1345	4	0	0
T7	4997	2	0	0
T8	1275	0	0	0
T9	54442	43	0	0
T10	1362	0	0	0
T11	0	1	0	0
T16	0	17	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	43535	0	0
T1	3969	3	0	0
T2	2692	5	0	0
T3	1129	3	0	0
T4	2405	13	0	0
T5	4716	5	0	0
T6	1345	5	0	0
T7	4997	3	0	0
T8	1275	4	0	0
T9	54442	44	0	0
T10	1362	7	0	0