Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24932165	6497	0	0
EscTimeoutStoppedByClReset_A	24931586	3389075	0	0
EscTimeoutTriggersReset_A	5580072	310	0	0
RomAllowActiveState_A	24931586	61421	0	0
RomAllowCheckGoodState_A	24931586	61471	0	0
RomBlockActiveState_A	24931586	33932	0	0
RomBlockCheckGoodState_A	24931586	457455	0	0
RomIntgChkDisFalse_A	24931586	24269798	0	0
RomIntgChkDisTrue_A	24931586	120356	0	0
RstreqChkEsctimeout_A	24931586	4593	0	0
RstreqChkFsmterm_A	24931586	160	0	0
RstreqChkGlbesc_A	24931586	4593	0	0
RstreqChkMainpd_A	24931586	1019184	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24932165	6497	0	0
T11	15665	174	0	0
T12	2441	0	0	0
T13	0	169	0	0
T14	8262	0	0	0
T15	5654	0	0	0
T17	1312	0	0	0
T20	7642	0	0	0
T27	13231	0	0	0
T39	789	0	0	0
T43	0	19	0	0
T44	0	2	0	0
T46	2667	0	0	0
T47	3379	0	0	0
T94	0	30	0	0
T151	0	264	0	0
T152	0	30	0	0
T153	0	95	0	0
T154	0	55	0	0
T155	0	57	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	3389075	0	0
T1	3969	16	0	0
T2	2692	72	0	0
T3	1129	13	0	0
T4	2405	0	0	0
T5	4716	524	0	0
T6	1345	49	0	0
T7	4997	20	0	0
T8	1275	37	0	0
T9	54442	10556	0	0
T10	1362	22	0	0
T16	0	25	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5580072	310	0	0
T11	199	2	0	0
T12	213	3	0	0
T13	0	2	0	0
T14	789	0	0	0
T15	418	0	0	0
T17	389	0	0	0
T20	890	0	0	0
T27	1400	0	0	0
T39	249	0	0	0
T43	0	2	0	0
T44	0	11	0	0
T46	979	0	0	0
T47	1400	0	0	0
T94	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	2	0	0
T156	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	61421	0	0
T1	3969	3	0	0
T2	2692	5	0	0
T3	1129	3	0	0
T4	2405	16	0	0
T5	4716	6	0	0
T6	1345	5	0	0
T7	4997	3	0	0
T8	1275	4	0	0
T9	54442	86	0	0
T10	1362	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	61471	0	0
T1	3969	3	0	0
T2	2692	5	0	0
T3	1129	3	0	0
T4	2405	16	0	0
T5	4716	6	0	0
T6	1345	5	0	0
T7	4997	3	0	0
T8	1275	4	0	0
T9	54442	86	0	0
T10	1362	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	33932	0	0
T12	2440	0	0	0
T13	15486	0	0	0
T15	5654	1227	0	0
T17	1311	0	0	0
T28	5463	1012	0	0
T29	4874	637	0	0
T32	0	8	0	0
T40	22036	12	0	0
T41	32636	0	0	0
T46	2666	0	0	0
T47	3378	0	0	0
T49	0	1221	0	0
T95	0	35	0	0
T100	0	1338	0	0
T157	0	624	0	0
T158	0	10	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	457455	0	0
T9	54442	4110	0	0
T10	1362	0	0	0
T11	15664	0	0	0
T12	2440	0	0	0
T14	8262	0	0	0
T15	5654	1095	0	0
T16	3322	0	0	0
T20	7641	161	0	0
T27	13230	0	0	0
T28	0	355	0	0
T29	0	573	0	0
T39	788	0	0	0
T40	0	1267	0	0
T41	0	2194	0	0
T49	0	985	0	0
T84	0	114	0	0
T86	0	92	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	24269798	0	0
T1	3969	3918	0	0
T2	2692	2328	0	0
T3	1129	1031	0	0
T4	2405	2318	0	0
T5	4716	4648	0	0
T6	1345	988	0	0
T7	4997	4919	0	0
T8	1275	995	0	0
T9	54442	54377	0	0
T10	1362	859	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	120356	0	0
T12	2440	0	0	0
T13	15486	0	0	0
T15	5654	252	0	0
T17	1311	0	0	0
T28	5463	311	0	0
T29	4874	834	0	0
T32	0	403	0	0
T40	22036	0	0	0
T41	32636	0	0	0
T46	2666	0	0	0
T47	3378	0	0	0
T49	0	2366	0	0
T95	0	389	0	0
T97	0	108	0	0
T100	0	478	0	0
T157	0	96	0	0
T159	0	29728	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	4593	0	0
T8	1275	3	0	0
T9	54442	0	0	0
T10	1362	0	0	0
T11	15664	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	8262	2	0	0
T15	5654	1	0	0
T16	3322	0	0	0
T20	7641	0	0	0
T27	13230	0	0	0
T28	0	3	0	0
T29	0	2	0	0
T39	788	0	0	0
T42	0	3	0	0
T48	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	160	0	0
T18	1131	0	0	0
T21	7552	20	0	0
T22	0	20	0	0
T23	0	40	0	0
T25	264773	0	0	0
T30	0	40	0	0
T31	0	40	0	0
T32	21109	0	0	0
T33	1657	0	0	0
T34	1344	0	0	0
T35	8955	0	0	0
T36	30707	0	0	0
T37	22025	0	0	0
T38	1849	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	4593	0	0
T8	1275	3	0	0
T9	54442	0	0	0
T10	1362	0	0	0
T11	15664	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	8262	2	0	0
T15	5654	1	0	0
T16	3322	0	0	0
T20	7641	0	0	0
T27	13230	0	0	0
T28	0	3	0	0
T29	0	2	0	0
T39	788	0	0	0
T42	0	3	0	0
T48	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24931586	1019184	0	0
T9	54442	4229	0	0
T10	1362	27	0	0
T11	15664	0	0	0
T12	2440	0	0	0
T14	8262	87	0	0
T15	5654	1910	0	0
T16	3322	0	0	0
T20	7641	453	0	0
T27	13230	0	0	0
T28	0	1097	0	0
T29	0	1182	0	0
T39	788	22	0	0
T40	0	1037	0	0
T41	0	1727	0	0