Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	498434	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183940

1

T1

192

T2

6

T3

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	351024	1			T1	409		T2	5		T3	101
values[0x0]	165053	1			T1	215		T2	7		T3	59
values[0x1]	166297	1			T1	237		T2	9		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	394687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

287687

1

T1

322

T2

8

T3

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2118	1			T1	5		T10	1		T76	1
valid_sources[0x01]	2066	1			T1	6		T3	1		T25	1
valid_sources[0x02]	4184	1			T1	4		T25	2		T38	3
valid_sources[0x03]	2122	1			T1	3		T3	1		T8	2
valid_sources[0x04]	2050	1			T1	3		T3	3		T4	5
valid_sources[0x05]	2295	1			T1	6		T37	1		T25	3
valid_sources[0x06]	2262	1			T1	1		T3	2		T5	14
valid_sources[0x07]	2523	1			T1	3		T38	2		T39	5
valid_sources[0x08]	3102	1			T3	4		T25	1		T54	1
valid_sources[0x09]	2599	1			T1	8		T3	2		T76	2
valid_sources[0x0a]	2854	1			T1	3		T3	2		T75	2
valid_sources[0x0b]	4394	1			T1	4		T3	1		T37	1
valid_sources[0x0c]	2094	1			T1	5		T3	2		T25	4
valid_sources[0x0d]	2279	1			T1	8		T9	3		T10	1
valid_sources[0x0e]	2114	1			T1	3		T37	1		T25	2
valid_sources[0x0f]	2260	1			T1	3		T3	1		T5	24
valid_sources[0x10]	2121	1			T1	4		T3	1		T5	14
valid_sources[0x11]	4015	1			T1	2		T6	1		T37	1
valid_sources[0x12]	2445	1			T1	1		T25	3		T13	3
valid_sources[0x13]	2628	1			T1	2		T6	1		T37	1
valid_sources[0x14]	3327	1			T1	3		T5	14		T37	1
valid_sources[0x15]	2347	1			T1	5		T3	2		T5	195
valid_sources[0x16]	2775	1			T1	3		T3	4		T5	13
valid_sources[0x17]	2325	1			T1	4		T5	12		T25	4
valid_sources[0x18]	2211	1			T1	2		T3	1		T5	13
valid_sources[0x19]	2102	1			T1	3		T25	2		T38	2
valid_sources[0x1a]	2259	1			T1	6		T6	1		T9	2
valid_sources[0x1b]	4024	1			T1	5		T3	2		T37	1
valid_sources[0x1c]	3100	1			T1	3		T3	1		T10	1
valid_sources[0x1d]	6931	1			T1	2		T4	1		T25	5
valid_sources[0x1e]	2436	1			T1	5		T3	1		T76	1
valid_sources[0x1f]	2684	1			T1	5		T75	2		T25	2
valid_sources[0x20]	4093	1			T1	2		T10	2		T25	3
valid_sources[0x21]	2091	1			T1	6		T3	1		T37	1
valid_sources[0x22]	3282	1			T1	3		T3	1		T8	8
valid_sources[0x23]	3946	1			T2	1		T25	1		T38	5
valid_sources[0x24]	2317	1			T1	1		T25	1		T38	2
valid_sources[0x25]	2212	1			T1	1		T3	1		T4	1
valid_sources[0x26]	2317	1			T1	1		T3	2		T76	1
valid_sources[0x27]	2119	1			T1	3		T25	3		T13	22
valid_sources[0x28]	2322	1			T1	3		T3	1		T4	2
valid_sources[0x29]	2017	1			T1	2		T25	3		T38	3
valid_sources[0x2a]	3076	1			T1	1		T25	2		T13	3
valid_sources[0x2b]	2191	1			T3	1		T5	15		T9	1
valid_sources[0x2c]	2436	1			T1	3		T5	12		T8	2
valid_sources[0x2d]	3899	1			T1	5		T3	2		T25	5
valid_sources[0x2e]	2386	1			T1	4		T9	2		T37	2
valid_sources[0x2f]	2953	1			T1	5		T3	1		T25	2
valid_sources[0x30]	2556	1			T1	3		T3	5		T37	1
valid_sources[0x31]	3556	1			T1	4		T3	1		T37	2
valid_sources[0x32]	2963	1			T1	4		T3	1		T25	1
valid_sources[0x33]	2523	1			T1	1		T2	1		T3	3
valid_sources[0x34]	2813	1			T3	2		T37	1		T25	4
valid_sources[0x35]	2158	1			T1	7		T3	1		T10	2
valid_sources[0x36]	2193	1			T1	4		T25	7		T38	3
valid_sources[0x37]	2221	1			T1	5		T6	1		T37	4
valid_sources[0x38]	2356	1			T1	7		T10	2		T25	4
valid_sources[0x39]	2538	1			T1	2		T3	1		T5	13
valid_sources[0x3a]	3137	1			T1	3		T5	1040		T25	1
valid_sources[0x3b]	2148	1			T1	5		T25	3		T38	6
valid_sources[0x3c]	2487	1			T1	3		T3	2		T5	13
valid_sources[0x3d]	3151	1			T5	12		T25	4		T13	13
valid_sources[0x3e]	2574	1			T1	6		T3	1		T10	1
valid_sources[0x3f]	2091	1			T1	6		T3	2		T25	5
valid_sources[0x40]	3080	1			T1	1		T3	1		T37	2
valid_sources[0x41]	2357	1			T1	2		T3	3		T6	3
valid_sources[0x42]	2451	1			T1	7		T3	1		T8	2
valid_sources[0x43]	3114	1			T1	1		T3	1		T37	2
valid_sources[0x44]	4809	1			T1	4		T3	1		T5	13
valid_sources[0x45]	2049	1			T1	2		T76	1		T25	2
valid_sources[0x46]	2105	1			T1	4		T25	1		T38	4
valid_sources[0x47]	2111	1			T1	2		T3	1		T8	1
valid_sources[0x48]	2253	1			T1	2		T3	1		T6	1
valid_sources[0x49]	2903	1			T1	2		T3	3		T6	1
valid_sources[0x4a]	2045	1			T1	1		T3	2		T4	7
valid_sources[0x4b]	2458	1			T1	3		T3	1		T4	5
valid_sources[0x4c]	2186	1			T1	2		T3	2		T76	1
valid_sources[0x4d]	2671	1			T1	3		T3	2		T25	2
valid_sources[0x4e]	2254	1			T1	2		T3	1		T37	3
valid_sources[0x4f]	5172	1			T1	6		T3	1		T9	1
valid_sources[0x50]	2178	1			T1	4		T3	1		T25	2
valid_sources[0x51]	4300	1			T1	3		T25	2		T54	2
valid_sources[0x52]	2242	1			T1	4		T25	2		T39	4
valid_sources[0x53]	2132	1			T1	3		T3	1		T9	3
valid_sources[0x54]	2615	1			T1	2		T3	1		T25	3
valid_sources[0x55]	2160	1			T1	1		T6	1		T76	1
valid_sources[0x56]	2277	1			T1	2		T76	1		T25	6
valid_sources[0x57]	2333	1			T3	3		T25	3		T38	2
valid_sources[0x58]	2748	1			T1	2		T54	2		T38	10
valid_sources[0x59]	2513	1			T1	5		T8	1		T10	1
valid_sources[0x5a]	2599	1			T1	2		T76	1		T25	7
valid_sources[0x5b]	2055	1			T1	5		T25	3		T38	1
valid_sources[0x5c]	2011	1			T1	4		T3	1		T10	2
valid_sources[0x5d]	2258	1			T1	3		T25	1		T13	13
valid_sources[0x5e]	3494	1			T1	3		T5	1212		T25	3
valid_sources[0x5f]	2384	1			T1	4		T3	1		T37	1
valid_sources[0x60]	2113	1			T1	5		T3	1		T10	1
valid_sources[0x61]	2860	1			T1	3		T5	13		T6	1
valid_sources[0x62]	2975	1			T1	5		T2	1		T37	1
valid_sources[0x63]	3983	1			T1	3		T3	2		T76	1
valid_sources[0x64]	2443	1			T1	4		T3	1		T25	4
valid_sources[0x65]	2200	1			T1	7		T10	1		T25	5
valid_sources[0x66]	2742	1			T1	3		T3	2		T25	5
valid_sources[0x67]	2198	1			T1	6		T3	1		T5	2
valid_sources[0x68]	2169	1			T1	5		T3	3		T75	2
valid_sources[0x69]	3473	1			T1	6		T2	1		T3	1
valid_sources[0x6a]	2304	1			T1	2		T4	3		T7	1
valid_sources[0x6b]	2284	1			T3	1		T25	1		T13	12
valid_sources[0x6c]	4829	1			T1	2		T37	1		T25	2
valid_sources[0x6d]	4469	1			T1	8		T37	1		T25	5
valid_sources[0x6e]	2220	1			T1	3		T25	4		T54	3
valid_sources[0x6f]	2032	1			T1	8		T4	4		T37	1
valid_sources[0x70]	2410	1			T1	3		T3	2		T37	1
valid_sources[0x71]	3657	1			T1	3		T37	1		T25	1
valid_sources[0x72]	2711	1			T1	2		T37	2		T25	3
valid_sources[0x73]	2270	1			T1	2		T25	1		T13	2
valid_sources[0x74]	2843	1			T1	3		T75	1		T25	4
valid_sources[0x75]	2207	1			T1	2		T3	1		T5	15
valid_sources[0x76]	2990	1			T1	3		T25	4		T14	2
valid_sources[0x77]	2189	1			T1	4		T10	3		T76	1
valid_sources[0x78]	2294	1			T1	6		T25	4		T13	338
valid_sources[0x79]	2155	1			T1	3		T76	1		T25	4
valid_sources[0x7a]	3880	1			T1	6		T37	1		T76	1
valid_sources[0x7b]	2346	1			T1	6		T3	1		T25	1
valid_sources[0x7c]	2548	1			T1	5		T3	2		T4	10
valid_sources[0x7d]	8450	1			T1	1		T2	1		T3	1
valid_sources[0x7e]	2137	1			T1	6		T10	1		T25	2
valid_sources[0x7f]	2106	1			T1	1		T3	1		T10	1
valid_sources[0x80]	2694	1			T1	1		T3	1		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89943

1

T1

82

T2

1

T3

18

values[0x0]

all_enables

biggest_size

61093

1

T1

72

T2

4

T3

22

values[0x1]

all_enables

biggest_size

32904

1

T1

38

T2

1

T3

12