SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34907 | 1 | T1 | 409 | T25 | 284 | T38 | 316 | ||||
others[1] | 34992 | 1 | T1 | 409 | T25 | 301 | T38 | 290 | ||||
others[2] | 35066 | 1 | T1 | 411 | T25 | 303 | T38 | 320 | ||||
others[3] | 58264 | 1 | T1 | 632 | T10 | 1 | T24 | 1 | ||||
false | 19181 | 1 | T1 | 50 | T5 | 114 | T10 | 3 | ||||
true | 29143 | 1 | T1 | 102 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34886 | 1 | T1 | 421 | T10 | 1 | T25 | 287 | ||||
others[1] | 35075 | 1 | T1 | 409 | T24 | 1 | T25 | 307 | ||||
others[2] | 35013 | 1 | T1 | 386 | T25 | 304 | T38 | 285 | ||||
others[3] | 58343 | 1 | T1 | 634 | T25 | 510 | T38 | 512 | ||||
false | 12185 | 1 | T1 | 50 | T5 | 57 | T10 | 4 | ||||
true | 22214 | 1 | T1 | 102 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 662 | 1 | T5 | 3 | T24 | 1 | T21 | 2 | ||||
others[1] | 658 | 1 | T4 | 1 | T5 | 8 | T37 | 1 | ||||
others[2] | 701 | 1 | T5 | 3 | T37 | 2 | T13 | 1 | ||||
others[3] | 1184 | 1 | T4 | 2 | T5 | 3 | T37 | 1 | ||||
false | 13533 | 1 | T1 | 2 | T2 | 5 | T3 | 1 | ||||
true | 3960 | 1 | T4 | 6 | T5 | 27 | T10 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |