Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23598301	6179	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23598301	252634	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23598301	9715628	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23598301	252622	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23598301	6179	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23598301	252634	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23598301	9715628	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23598301	252622	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	6179	0	0
T1	58864	25	0	0
T2	1632	3	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	26	0	0
T6	1397	1	0	0
T7	1249	0	0	0
T8	3026	3	0	0
T9	3322	2	0	0
T10	5269	0	0	0
T13	0	20	0	0
T25	0	23	0	0
T75	0	1	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	252634	0	0
T1	58864	1692	0	0
T2	1632	269	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	1096	0	0
T6	1397	12	0	0
T7	1249	0	0	0
T8	3026	708	0	0
T9	3322	541	0	0
T10	5269	0	0	0
T13	0	645	0	0
T25	0	607	0	0
T75	0	11	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	9715628	0	0
T1	58864	35025	0	0
T2	1632	854	0	0
T3	5265	512	0	0
T4	4195	0	0	0
T5	95277	37492	0	0
T6	1397	1089	0	0
T7	1249	0	0	0
T8	3026	869	0	0
T9	3322	366	0	0
T10	5269	0	0	0
T40	0	5042	0	0
T75	0	1416	0	0
T76	0	748	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	252622	0	0
T1	58864	1692	0	0
T2	1632	269	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	1096	0	0
T6	1397	12	0	0
T7	1249	0	0	0
T8	3026	708	0	0
T9	3322	541	0	0
T10	5269	0	0	0
T13	0	645	0	0
T25	0	607	0	0
T75	0	11	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	6179	0	0
T1	58864	25	0	0
T2	1632	3	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	26	0	0
T6	1397	1	0	0
T7	1249	0	0	0
T8	3026	3	0	0
T9	3322	2	0	0
T10	5269	0	0	0
T13	0	20	0	0
T25	0	23	0	0
T75	0	1	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	252634	0	0
T1	58864	1692	0	0
T2	1632	269	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	1096	0	0
T6	1397	12	0	0
T7	1249	0	0	0
T8	3026	708	0	0
T9	3322	541	0	0
T10	5269	0	0	0
T13	0	645	0	0
T25	0	607	0	0
T75	0	11	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	9715628	0	0
T1	58864	35025	0	0
T2	1632	854	0	0
T3	5265	512	0	0
T4	4195	0	0	0
T5	95277	37492	0	0
T6	1397	1089	0	0
T7	1249	0	0	0
T8	3026	869	0	0
T9	3322	366	0	0
T10	5269	0	0	0
T40	0	5042	0	0
T75	0	1416	0	0
T76	0	748	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	252622	0	0
T1	58864	1692	0	0
T2	1632	269	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	1096	0	0
T6	1397	12	0	0
T7	1249	0	0	0
T8	3026	708	0	0
T9	3322	541	0	0
T10	5269	0	0	0
T13	0	645	0	0
T25	0	607	0	0
T75	0	11	0	0
T76	0	12	0	0