Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24147740	12952	0	0
intr_enable_rd_A	24147740	56927	0	0
reset_en_rd_A	24147740	849	0	0
reset_en_regwen_rd_A	24147740	722	0	0
wake_info_capture_dis_rd_A	24147740	819	0	0
wakeup_en_rd_A	24147740	1587	0	0
wakeup_en_regwen_rd_A	24147740	676	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	12952	0	0
T12	15305	0	0	0
T21	457174	17	0	0
T22	0	23	0	0
T23	0	29	0	0
T32	0	24	0	0
T43	4482	0	0	0
T48	0	50	0	0
T77	3014	0	0	0
T136	0	5	0	0
T137	0	6	0	0
T138	0	17	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	56927	0	0
T1	58864	165	0	0
T2	1632	0	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	0	0	0
T6	1397	0	0	0
T7	1249	0	0	0
T8	3026	0	0	0
T9	3322	0	0	0
T10	5269	0	0	0
T13	0	575	0	0
T21	0	1777	0	0
T22	0	3061	0	0
T23	0	1002	0	0
T37	0	38	0	0
T56	0	14	0	0
T75	0	2	0	0
T77	0	10	0	0
T146	0	26	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	849	0	0
T12	15305	0	0	0
T21	457174	2	0	0
T22	0	17	0	0
T23	0	17	0	0
T43	4482	0	0	0
T77	3014	0	0	0
T81	0	13	0	0
T83	0	13	0	0
T138	0	18	0	0
T139	0	17	0	0
T140	0	7	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0
T147	0	4	0	0
T148	0	8	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	722	0	0
T12	15305	0	0	0
T21	457174	1	0	0
T22	0	4	0	0
T23	0	5	0	0
T43	4482	0	0	0
T77	3014	0	0	0
T81	0	10	0	0
T83	0	5	0	0
T138	0	6	0	0
T139	0	20	0	0
T140	0	3	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0
T148	0	9	0	0
T149	0	6	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	819	0	0
T12	15305	0	0	0
T21	457174	9	0	0
T22	0	7	0	0
T43	4482	0	0	0
T77	3014	0	0	0
T81	0	14	0	0
T83	0	10	0	0
T138	0	9	0	0
T139	0	19	0	0
T140	0	2	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	1587	0	0
T12	15305	0	0	0
T21	457174	1	0	0
T22	0	24	0	0
T23	0	2	0	0
T43	4482	0	0	0
T77	3014	0	0	0
T81	0	17	0	0
T83	0	9	0	0
T136	0	7	0	0
T138	0	1	0	0
T139	0	16	0	0
T140	0	10	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0
T148	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24147740	676	0	0
T12	15305	0	0	0
T21	457174	5	0	0
T22	0	3	0	0
T23	0	2	0	0
T43	4482	0	0	0
T77	3014	0	0	0
T81	0	17	0	0
T83	0	7	0	0
T138	0	5	0	0
T139	0	20	0	0
T140	0	2	0	0
T141	1483	0	0	0
T142	1176	0	0	0
T143	2343	0	0	0
T144	1322	0	0	0
T145	2742	0	0	0
T146	5738	0	0	0
T148	0	3	0	0
T149	0	1	0	0