Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70794903	143055	0	0
StatusRise_A	70794903	159710	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70794903	143055	0	0
T1	176592	215	0	0
T2	4896	12	0	0
T3	15795	43	0	0
T4	12585	54	0	0
T5	285831	681	0	0
T6	4191	6	0	0
T7	3747	3	0	0
T8	9078	12	0	0
T9	9966	12	0	0
T10	15807	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70794903	159710	0	0
T1	176592	220	0	0
T2	4896	15	0	0
T3	15795	45	0	0
T4	12585	57	0	0
T5	285831	753	0	0
T6	4191	9	0	0
T7	3747	9	0	0
T8	9078	15	0	0
T9	9966	15	0	0
T10	15807	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23598301	53105	0	0
StatusRise_A	23598301	59123	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	53105	0	0
T1	58864	82	0	0
T2	1632	4	0	0
T3	5265	16	0	0
T4	4195	18	0	0
T5	95277	255	0	0
T6	1397	2	0	0
T7	1249	1	0	0
T8	3026	4	0	0
T9	3322	4	0	0
T10	5269	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	59123	0	0
T1	58864	84	0	0
T2	1632	5	0	0
T3	5265	17	0	0
T4	4195	19	0	0
T5	95277	281	0	0
T6	1397	3	0	0
T7	1249	3	0	0
T8	3026	5	0	0
T9	3322	5	0	0
T10	5269	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23598301	53105	0	0
StatusRise_A	23598301	59123	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	53105	0	0
T1	58864	82	0	0
T2	1632	4	0	0
T3	5265	16	0	0
T4	4195	18	0	0
T5	95277	255	0	0
T6	1397	2	0	0
T7	1249	1	0	0
T8	3026	4	0	0
T9	3322	4	0	0
T10	5269	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	59123	0	0
T1	58864	84	0	0
T2	1632	5	0	0
T3	5265	17	0	0
T4	4195	19	0	0
T5	95277	281	0	0
T6	1397	3	0	0
T7	1249	3	0	0
T8	3026	5	0	0
T9	3322	5	0	0
T10	5269	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23598301	36845	0	0
StatusRise_A	23598301	41464	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	36845	0	0
T1	58864	51	0	0
T2	1632	4	0	0
T3	5265	11	0	0
T4	4195	18	0	0
T5	95277	171	0	0
T6	1397	2	0	0
T7	1249	1	0	0
T8	3026	4	0	0
T9	3322	4	0	0
T10	5269	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	41464	0	0
T1	58864	52	0	0
T2	1632	5	0	0
T3	5265	11	0	0
T4	4195	19	0	0
T5	95277	191	0	0
T6	1397	3	0	0
T7	1249	3	0	0
T8	3026	5	0	0
T9	3322	5	0	0
T10	5269	6	0	0