Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23598910	6539	0	0
EscTimeoutStoppedByClReset_A	23598301	3223765	0	0
EscTimeoutTriggersReset_A	4979164	333	0	0
RomAllowActiveState_A	23598301	58729	0	0
RomAllowCheckGoodState_A	23598301	58781	0	0
RomBlockActiveState_A	23598301	28575	0	0
RomBlockCheckGoodState_A	23598301	419605	0	0
RomIntgChkDisFalse_A	23598301	22979594	0	0
RomIntgChkDisTrue_A	23598301	99380	0	0
RstreqChkEsctimeout_A	23598301	4161	0	0
RstreqChkFsmterm_A	23598301	160	0	0
RstreqChkGlbesc_A	23598301	4161	0	0
RstreqChkMainpd_A	23598301	929570	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598910	6539	0	0
T7	1250	10	0	0
T8	3027	0	0	0
T9	3323	0	0	0
T10	5269	0	0	0
T11	0	37	0	0
T12	0	145	0	0
T24	2015	0	0	0
T37	3854	0	0	0
T40	10815	0	0	0
T41	1641	0	0	0
T75	2330	0	0	0
T76	944	0	0	0
T151	0	169	0	0
T152	0	182	0	0
T153	0	3	0	0
T154	0	230	0	0
T155	0	174	0	0
T156	0	270	0	0
T157	0	272	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	3223765	0	0
T1	58864	8286	0	0
T2	1632	51	0	0
T3	5265	1594	0	0
T4	4195	356	0	0
T5	95277	13889	0	0
T6	1397	12	0	0
T7	1249	56	0	0
T8	3026	38	0	0
T9	3322	104	0	0
T10	5269	64	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4979164	333	0	0
T7	219	4	0	0
T8	287	0	0	0
T9	325	0	0	0
T10	395	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T24	662	0	0	0
T37	555	0	0	0
T40	1234	0	0	0
T41	536	0	0	0
T75	208	0	0	0
T76	776	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	2	0	0
T158	0	3	0	0
T159	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	58729	0	0
T1	58864	84	0	0
T2	1632	5	0	0
T3	5265	17	0	0
T4	4195	12	0	0
T5	95277	281	0	0
T6	1397	3	0	0
T7	1249	3	0	0
T8	3026	5	0	0
T9	3322	5	0	0
T10	5269	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	58781	0	0
T1	58864	84	0	0
T2	1632	5	0	0
T3	5265	17	0	0
T4	4195	13	0	0
T5	95277	281	0	0
T6	1397	3	0	0
T7	1249	3	0	0
T8	3026	5	0	0
T9	3322	5	0	0
T10	5269	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	28575	0	0
T10	5269	1214	0	0
T13	95222	0	0	0
T24	2014	138	0	0
T25	21482	9	0	0
T37	3853	0	0	0
T38	0	7	0	0
T40	10815	0	0	0
T41	1640	0	0	0
T54	2550	0	0	0
T75	2329	0	0	0
T76	944	0	0	0
T78	0	1	0	0
T160	0	884	0	0
T161	0	253	0	0
T162	0	86	0	0
T163	0	149	0	0
T164	0	5	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	419605	0	0
T1	58864	4061	0	0
T2	1632	0	0	0
T3	5265	0	0	0
T4	4195	0	0	0
T5	95277	1304	0	0
T6	1397	0	0	0
T7	1249	0	0	0
T8	3026	0	0	0
T9	3322	0	0	0
T10	5269	1097	0	0
T13	0	711	0	0
T21	0	3947	0	0
T24	0	51	0	0
T25	0	1287	0	0
T38	0	1328	0	0
T39	0	4118	0	0
T78	0	672	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	22979594	0	0
T1	58864	58711	0	0
T2	1632	1230	0	0
T3	5265	5171	0	0
T4	4195	3362	0	0
T5	95277	93494	0	0
T6	1397	1299	0	0
T7	1249	1122	0	0
T8	3026	2603	0	0
T9	3322	2949	0	0
T10	5269	5177	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	99380	0	0
T13	95222	0	0	0
T14	9794	0	0	0
T24	2014	142	0	0
T25	21482	405	0	0
T38	17220	377	0	0
T39	53119	2400	0	0
T54	2550	0	0	0
T75	2329	0	0	0
T76	944	0	0	0
T78	0	144	0	0
T160	0	485	0	0
T161	0	640	0	0
T162	0	842	0	0
T163	0	1134	0	0
T165	0	3611	0	0
T166	3157	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	4161	0	0
T4	4195	6	0	0
T5	95277	31	0	0
T6	1397	0	0	0
T7	1249	1	0	0
T8	3026	0	0	0
T9	3322	0	0	0
T10	5269	3	0	0
T13	0	4	0	0
T14	0	9	0	0
T24	0	3	0	0
T37	3853	5	0	0
T40	10815	0	0	0
T41	1640	4	0	0
T42	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	160	0	0
T18	44963	40	0	0
T19	0	20	0	0
T20	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	2443	0	0	0
T29	21596	0	0	0
T30	2844	0	0	0
T31	4719	0	0	0
T32	254659	0	0	0
T33	21374	0	0	0
T34	21598	0	0	0
T35	1573	0	0	0
T36	4128	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	4161	0	0
T4	4195	6	0	0
T5	95277	31	0	0
T6	1397	0	0	0
T7	1249	1	0	0
T8	3026	0	0	0
T9	3322	0	0	0
T10	5269	3	0	0
T13	0	4	0	0
T14	0	9	0	0
T24	0	3	0	0
T37	3853	5	0	0
T40	10815	0	0	0
T41	1640	4	0	0
T42	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23598301	929570	0	0
T1	58864	6158	0	0
T2	1632	0	0	0
T3	5265	0	0	0
T4	4195	124	0	0
T5	95277	5198	0	0
T6	1397	0	0	0
T7	1249	0	0	0
T8	3026	0	0	0
T9	3322	0	0	0
T10	5269	0	0	0
T13	0	1663	0	0
T14	0	520	0	0
T24	0	75	0	0
T25	0	1867	0	0
T37	0	207	0	0
T38	0	1395	0	0
T39	0	5813	0	0