Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	505591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

193325

1

T1

23

T2

1

T3

5731

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	367677	1			T1	47		T2	1		T3	10814
values[0x0]	165336	1			T1	24		T3	3286		T7	33
values[0x1]	165903	1			T1	26		T3	3176		T7	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	400416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

298500

1

T1

42

T2

1

T3

8062

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2208	1			T3	99		T11	3		T12	3
valid_sources[0x01]	2327	1			T3	58		T7	2		T11	4
valid_sources[0x02]	2552	1			T3	29		T7	3		T11	5
valid_sources[0x03]	3158	1			T3	86		T7	1		T11	3
valid_sources[0x04]	2282	1			T3	68		T11	3		T23	2
valid_sources[0x05]	2008	1			T3	70		T11	1		T12	3
valid_sources[0x06]	3775	1			T3	50		T11	4		T13	2
valid_sources[0x07]	2734	1			T3	115		T11	7		T12	4
valid_sources[0x08]	2268	1			T3	51		T9	10		T12	3
valid_sources[0x09]	2750	1			T3	57		T7	1		T11	4
valid_sources[0x0a]	2065	1			T3	53		T13	2		T37	1
valid_sources[0x0b]	3127	1			T3	86		T11	5		T23	1
valid_sources[0x0c]	1997	1			T3	70		T11	3		T12	5
valid_sources[0x0d]	2647	1			T3	64		T7	1		T11	6
valid_sources[0x0e]	2536	1			T3	45		T9	4		T11	4
valid_sources[0x0f]	3186	1			T3	73		T7	3		T11	4
valid_sources[0x10]	2324	1			T3	73		T7	2		T9	4
valid_sources[0x11]	2282	1			T3	77		T11	2		T13	1
valid_sources[0x12]	3199	1			T3	55		T9	1		T11	1
valid_sources[0x13]	2093	1			T3	56		T11	2		T74	1
valid_sources[0x14]	5244	1			T3	64		T7	1		T11	4
valid_sources[0x15]	4029	1			T3	46		T7	2		T11	1
valid_sources[0x16]	3600	1			T3	48		T9	1		T11	5
valid_sources[0x17]	2434	1			T3	38		T7	1		T11	2
valid_sources[0x18]	1943	1			T3	72		T7	3		T11	4
valid_sources[0x19]	2693	1			T3	43		T11	4		T12	3
valid_sources[0x1a]	2112	1			T3	86		T11	2		T12	3
valid_sources[0x1b]	3117	1			T3	40		T9	2		T11	6
valid_sources[0x1c]	5035	1			T3	84		T7	1		T9	1
valid_sources[0x1d]	2458	1			T3	58		T9	7		T11	2
valid_sources[0x1e]	2968	1			T3	69		T7	1		T10	10
valid_sources[0x1f]	3717	1			T3	69		T11	5		T12	1
valid_sources[0x20]	2268	1			T3	74		T9	4		T11	8
valid_sources[0x21]	2320	1			T3	55		T11	5		T13	1
valid_sources[0x22]	2248	1			T3	98		T7	2		T10	101
valid_sources[0x23]	4464	1			T3	76		T7	2		T11	1
valid_sources[0x24]	2212	1			T3	58		T11	2		T13	1
valid_sources[0x25]	4534	1			T3	81		T7	1		T11	4
valid_sources[0x26]	2341	1			T3	64		T11	2		T13	1
valid_sources[0x27]	3112	1			T3	75		T9	12		T74	6
valid_sources[0x28]	2083	1			T3	54		T11	3		T23	2
valid_sources[0x29]	2277	1			T3	74		T11	3		T12	1
valid_sources[0x2a]	2060	1			T3	106		T11	3		T12	1
valid_sources[0x2b]	2184	1			T3	43		T11	4		T12	1
valid_sources[0x2c]	2623	1			T3	84		T9	2		T11	4
valid_sources[0x2d]	2228	1			T3	42		T7	2		T11	2
valid_sources[0x2e]	4096	1			T3	44		T11	2		T13	1
valid_sources[0x2f]	2657	1			T3	83		T9	2		T11	1
valid_sources[0x30]	4717	1			T3	55		T7	1		T9	3
valid_sources[0x31]	2253	1			T3	63		T9	7		T11	7
valid_sources[0x32]	3481	1			T3	79		T7	2		T11	2
valid_sources[0x33]	2467	1			T3	78		T9	4		T11	4
valid_sources[0x34]	2104	1			T3	67		T11	2		T37	8
valid_sources[0x35]	2333	1			T3	86		T7	3		T11	3
valid_sources[0x36]	2077	1			T3	66		T7	1		T11	3
valid_sources[0x37]	4722	1			T3	45		T7	3		T9	3
valid_sources[0x38]	2219	1			T3	74		T7	2		T10	4
valid_sources[0x39]	2210	1			T3	91		T7	2		T9	5
valid_sources[0x3a]	1948	1			T3	80		T11	5		T12	2
valid_sources[0x3b]	1951	1			T3	30		T11	2		T37	1
valid_sources[0x3c]	6134	1			T3	40		T10	2		T11	4
valid_sources[0x3d]	2386	1			T3	91		T11	2		T37	3
valid_sources[0x3e]	2273	1			T3	51		T11	5		T12	3
valid_sources[0x3f]	2347	1			T3	42		T11	7		T12	4
valid_sources[0x40]	2073	1			T3	52		T11	4		T12	2
valid_sources[0x41]	2392	1			T3	83		T9	4		T11	5
valid_sources[0x42]	2361	1			T3	79		T7	1		T11	3
valid_sources[0x43]	4238	1			T3	64		T11	4		T37	2
valid_sources[0x44]	3012	1			T3	70		T7	3		T11	3
valid_sources[0x45]	3279	1			T3	85		T11	2		T37	2
valid_sources[0x46]	2171	1			T3	59		T11	3		T12	2
valid_sources[0x47]	2199	1			T3	71		T11	5		T12	1
valid_sources[0x48]	2564	1			T3	61		T11	2		T12	1
valid_sources[0x49]	2206	1			T3	60		T7	1		T9	2
valid_sources[0x4a]	2148	1			T3	79		T7	1		T11	1
valid_sources[0x4b]	2472	1			T3	50		T7	3		T11	1
valid_sources[0x4c]	3650	1			T3	71		T7	2		T10	6
valid_sources[0x4d]	1980	1			T3	60		T7	1		T11	3
valid_sources[0x4e]	2362	1			T3	64		T11	4		T13	1
valid_sources[0x4f]	2538	1			T3	73		T7	2		T11	1
valid_sources[0x50]	2256	1			T3	65		T12	9		T13	1
valid_sources[0x51]	3063	1			T3	61		T7	2		T11	1
valid_sources[0x52]	1968	1			T3	88		T7	2		T9	1
valid_sources[0x53]	2009	1			T3	63		T7	2		T11	3
valid_sources[0x54]	2293	1			T3	59		T7	1		T11	4
valid_sources[0x55]	2054	1			T3	42		T7	3		T11	4
valid_sources[0x56]	4073	1			T3	94		T11	5		T13	2
valid_sources[0x57]	3150	1			T3	53		T11	4		T12	1
valid_sources[0x58]	3545	1			T3	51		T11	6		T13	1
valid_sources[0x59]	2197	1			T3	62		T7	1		T10	39
valid_sources[0x5a]	2169	1			T3	103		T7	1		T11	5
valid_sources[0x5b]	4831	1			T3	53		T7	4		T11	7
valid_sources[0x5c]	2850	1			T3	73		T11	4		T13	3
valid_sources[0x5d]	2009	1			T3	42		T7	1		T9	5
valid_sources[0x5e]	2014	1			T3	44		T11	6		T12	1
valid_sources[0x5f]	2986	1			T3	76		T11	4		T12	1
valid_sources[0x60]	2197	1			T3	63		T7	1		T9	14
valid_sources[0x61]	2339	1			T3	96		T11	4		T13	3
valid_sources[0x62]	2332	1			T3	85		T11	4		T12	1
valid_sources[0x63]	2189	1			T3	96		T11	4		T12	5
valid_sources[0x64]	4023	1			T3	68		T7	1		T11	2
valid_sources[0x65]	1892	1			T3	49		T7	1		T10	11
valid_sources[0x66]	2226	1			T3	76		T7	4		T11	3
valid_sources[0x67]	2582	1			T3	85		T7	1		T9	1
valid_sources[0x68]	2704	1			T3	60		T9	8		T11	8
valid_sources[0x69]	2922	1			T3	65		T11	3		T37	2
valid_sources[0x6a]	3479	1			T3	82		T7	3		T11	2
valid_sources[0x6b]	2235	1			T3	64		T11	1		T13	1
valid_sources[0x6c]	2405	1			T3	73		T7	4		T11	4
valid_sources[0x6d]	2242	1			T3	69		T7	5		T11	3
valid_sources[0x6e]	4675	1			T3	81		T7	1		T11	3
valid_sources[0x6f]	1975	1			T3	87		T7	2		T11	6
valid_sources[0x70]	2523	1			T3	94		T7	1		T9	2
valid_sources[0x71]	3094	1			T3	76		T11	3		T12	3
valid_sources[0x72]	2161	1			T3	54		T7	6		T11	7
valid_sources[0x73]	2172	1			T3	37		T7	2		T11	1
valid_sources[0x74]	3062	1			T3	74		T7	1		T9	2
valid_sources[0x75]	3163	1			T3	70		T11	2		T12	3
valid_sources[0x76]	2696	1			T3	80		T9	14		T11	4
valid_sources[0x77]	3440	1			T3	67		T11	2		T17	22
valid_sources[0x78]	2026	1			T3	68		T11	7		T37	1
valid_sources[0x79]	2901	1			T3	59		T7	2		T9	6
valid_sources[0x7a]	2029	1			T3	79		T7	2		T9	7
valid_sources[0x7b]	3098	1			T1	97		T3	36		T11	2
valid_sources[0x7c]	2376	1			T3	88		T11	3		T74	2
valid_sources[0x7d]	2021	1			T3	86		T9	10		T11	2
valid_sources[0x7e]	2482	1			T3	59		T9	5		T11	4
valid_sources[0x7f]	1904	1			T3	68		T11	6		T37	2
valid_sources[0x80]	2157	1			T3	83		T7	1		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

98071

1

T1

10

T2

1

T3

3891

values[0x0]

all_enables

biggest_size

61595

1

T1

10

T3

1229

T7

10

values[0x1]

all_enables

biggest_size

33659

1

T1

3

T3

611

T7

5