SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34697 | 1 | T11 | 386 | T23 | 292 | T36 | 406 | ||||
others[1] | 35152 | 1 | T11 | 382 | T22 | 1 | T23 | 304 | ||||
others[2] | 35160 | 1 | T11 | 411 | T23 | 292 | T36 | 387 | ||||
others[3] | 58444 | 1 | T11 | 682 | T23 | 498 | T36 | 660 | ||||
false | 18827 | 1 | T3 | 430 | T8 | 18 | T11 | 50 | ||||
true | 28796 | 1 | T1 | 1 | T2 | 5 | T3 | 540 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34869 | 1 | T11 | 401 | T23 | 297 | T36 | 394 | ||||
others[1] | 35071 | 1 | T11 | 378 | T23 | 302 | T36 | 386 | ||||
others[2] | 34969 | 1 | T11 | 430 | T22 | 2 | T23 | 313 | ||||
others[3] | 58593 | 1 | T11 | 666 | T23 | 479 | T36 | 659 | ||||
false | 12027 | 1 | T3 | 215 | T8 | 9 | T11 | 50 | ||||
true | 22049 | 1 | T1 | 1 | T2 | 5 | T3 | 325 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 710 | 1 | T3 | 7 | T7 | 6 | T9 | 3 | ||||
others[1] | 712 | 1 | T3 | 8 | T7 | 5 | T9 | 7 | ||||
others[2] | 694 | 1 | T3 | 9 | T7 | 6 | T9 | 3 | ||||
others[3] | 1105 | 1 | T3 | 6 | T7 | 9 | T9 | 10 | ||||
false | 13717 | 1 | T1 | 1 | T2 | 5 | T3 | 192 | ||||
true | 4105 | 1 | T3 | 52 | T9 | 3 | T10 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |