Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T23

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24358090	6250	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24358090	262538	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24358090	10091213	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24358090	262570	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24358090	6250	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24358090	262538	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24358090	10091213	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24358090	262570	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	6250	0	0
T3	647834	111	0	0
T7	4640	0	0	0
T8	3237	3	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	22	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	21	0	0
T21	0	59	0	0
T22	4066	0	0	0
T23	0	20	0	0
T36	0	26	0	0
T37	11007	0	0	0
T42	0	1	0	0
T72	0	8	0	0
T73	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	262538	0	0
T3	647834	7754	0	0
T7	4640	0	0	0
T8	3237	60	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	1133	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	1234	0	0
T21	0	3746	0	0
T22	4066	0	0	0
T23	0	526	0	0
T36	0	514	0	0
T37	11007	0	0	0
T42	0	108	0	0
T72	0	573	0	0
T73	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	10091213	0	0
T1	2164	1719	0	0
T2	1784	0	0	0
T3	647834	291522	0	0
T7	4640	0	0	0
T8	3237	889	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	23407	0	0
T12	3888	1560	0	0
T13	3197	0	0	0
T17	0	97200	0	0
T23	0	9311	0	0
T37	0	5271	0	0
T53	0	4348	0	0
T74	0	2677	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	262570	0	0
T3	647834	7754	0	0
T7	4640	0	0	0
T8	3237	60	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	1133	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	1234	0	0
T21	0	3750	0	0
T22	4066	0	0	0
T23	0	526	0	0
T36	0	514	0	0
T37	11007	0	0	0
T42	0	108	0	0
T72	0	573	0	0
T73	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	6250	0	0
T3	647834	111	0	0
T7	4640	0	0	0
T8	3237	3	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	22	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	21	0	0
T21	0	59	0	0
T22	4066	0	0	0
T23	0	20	0	0
T36	0	26	0	0
T37	11007	0	0	0
T42	0	1	0	0
T72	0	8	0	0
T73	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	262538	0	0
T3	647834	7754	0	0
T7	4640	0	0	0
T8	3237	60	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	1133	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	1234	0	0
T21	0	3746	0	0
T22	4066	0	0	0
T23	0	526	0	0
T36	0	514	0	0
T37	11007	0	0	0
T42	0	108	0	0
T72	0	573	0	0
T73	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	10091213	0	0
T1	2164	1719	0	0
T2	1784	0	0	0
T3	647834	291522	0	0
T7	4640	0	0	0
T8	3237	889	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	23407	0	0
T12	3888	1560	0	0
T13	3197	0	0	0
T17	0	97200	0	0
T23	0	9311	0	0
T37	0	5271	0	0
T53	0	4348	0	0
T74	0	2677	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	262570	0	0
T3	647834	7754	0	0
T7	4640	0	0	0
T8	3237	60	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	1133	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	1234	0	0
T21	0	3750	0	0
T22	4066	0	0	0
T23	0	526	0	0
T36	0	514	0	0
T37	11007	0	0	0
T42	0	108	0	0
T72	0	573	0	0
T73	0	12	0	0