Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24927800	15621	0	0
intr_enable_rd_A	24927800	37480	0	0
reset_en_rd_A	24927800	1884	0	0
reset_en_regwen_rd_A	24927800	1815	0	0
wake_info_capture_dis_rd_A	24927800	1806	0	0
wakeup_en_rd_A	24927800	2611	0	0
wakeup_en_regwen_rd_A	24927800	1815	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	15621	0	0
T3	647834	151	0	0
T7	4640	0	0	0
T8	3237	0	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	0	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	13	0	0
T21	0	28	0	0
T22	4066	0	0	0
T37	11007	0	0	0
T48	0	23	0	0
T49	0	32	0	0
T78	0	6	0	0
T119	0	3	0	0
T120	0	12	0	0
T121	0	7	0	0
T122	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	37480	0	0
T17	223363	612	0	0
T22	4066	0	0	0
T23	22412	0	0	0
T24	2907	0	0	0
T36	16055	0	0	0
T37	11007	48	0	0
T38	2294	0	0	0
T41	1767	0	0	0
T53	8581	0	0	0
T72	0	61	0	0
T73	0	7	0	0
T74	6377	0	0	0
T75	0	18	0	0
T77	0	576	0	0
T119	0	1851	0	0
T123	0	47	0	0
T124	0	44	0	0
T125	0	225	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	1884	0	0
T17	223363	8	0	0
T18	2277	0	0	0
T21	277145	0	0	0
T24	2907	0	0	0
T36	16055	0	0	0
T38	2294	0	0	0
T42	1752	0	0	0
T46	0	8	0	0
T72	20117	0	0	0
T75	6792	0	0	0
T80	0	9	0	0
T88	1767	0	0	0
T119	0	4	0	0
T126	0	9	0	0
T127	0	3	0	0
T128	0	7	0	0
T129	0	5	0	0
T130	0	9	0	0
T131	0	3	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	1815	0	0
T46	0	8	0	0
T47	0	46	0	0
T48	0	3	0	0
T58	0	61	0	0
T80	0	11	0	0
T119	278481	1	0	0
T124	4242	0	0	0
T125	24581	0	0	0
T126	0	8	0	0
T129	0	6	0	0
T130	0	14	0	0
T131	0	3	0	0
T132	997	0	0	0
T133	4750	0	0	0
T134	2974	0	0	0
T135	798	0	0	0
T136	3029	0	0	0
T137	3244	0	0	0
T138	1557	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	1806	0	0
T17	223363	7	0	0
T18	2277	0	0	0
T21	277145	0	0	0
T24	2907	0	0	0
T36	16055	0	0	0
T38	2294	0	0	0
T42	1752	0	0	0
T46	0	14	0	0
T48	0	6	0	0
T72	20117	0	0	0
T75	6792	0	0	0
T80	0	7	0	0
T88	1767	0	0	0
T126	0	6	0	0
T127	0	5	0	0
T128	0	3	0	0
T129	0	15	0	0
T130	0	9	0	0
T131	0	6	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	2611	0	0
T17	223363	6	0	0
T18	2277	0	0	0
T21	277145	0	0	0
T24	2907	0	0	0
T36	16055	0	0	0
T38	2294	0	0	0
T42	1752	0	0	0
T46	0	13	0	0
T47	0	116	0	0
T48	0	2	0	0
T72	20117	0	0	0
T75	6792	0	0	0
T80	0	2	0	0
T88	1767	0	0	0
T126	0	6	0	0
T128	0	4	0	0
T129	0	8	0	0
T130	0	17	0	0
T131	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24927800	1815	0	0
T17	223363	2	0	0
T18	2277	0	0	0
T21	277145	0	0	0
T24	2907	0	0	0
T36	16055	0	0	0
T38	2294	0	0	0
T42	1752	0	0	0
T48	0	3	0	0
T72	20117	0	0	0
T75	6792	0	0	0
T80	0	14	0	0
T88	1767	0	0	0
T119	0	7	0	0
T122	0	3	0	0
T127	0	5	0	0
T128	0	11	0	0
T129	0	9	0	0
T130	0	9	0	0
T131	0	3	0	0