Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_dft_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_hw_debug_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1910	1910	0	0
OutputsKnown_A	48716180	47678354	0	0
gen_flops.OutputDelay_A	48716180	47636636	0	5730

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1910	1910	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48716180	47678354	0	0
T1	4328	4138	0	0
T2	3568	2782	0	0
T3	1295668	1279404	0	0
T7	9280	9142	0	0
T8	6474	6332	0	0
T9	3454	3304	0	0
T10	14422	12520	0	0
T11	109172	108836	0	0
T12	7776	7630	0	0
T13	6394	6258	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48716180	47636636	0	5730
T1	4328	4132	0	6
T2	3568	2752	0	6
T3	1295668	1278744	0	6
T7	9280	9136	0	6
T8	6474	6326	0	6
T9	3454	3298	0	6
T10	14422	12442	0	6
T11	109172	108824	0	6
T12	7776	7624	0	6
T13	6394	6252	0	6

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	955	955	0	0
OutputsKnown_A	24358090	23839177	0	0
gen_flops.OutputDelay_A	24358090	23818318	0	2865

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	23839177	0	0
T1	2164	2069	0	0
T2	1784	1391	0	0
T3	647834	639702	0	0
T7	4640	4571	0	0
T8	3237	3166	0	0
T9	1727	1652	0	0
T10	7211	6260	0	0
T11	54586	54418	0	0
T12	3888	3815	0	0
T13	3197	3129	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	23818318	0	2865
T1	2164	2066	0	3
T2	1784	1376	0	3
T3	647834	639372	0	3
T7	4640	4568	0	3
T8	3237	3163	0	3
T9	1727	1649	0	3
T10	7211	6221	0	3
T11	54586	54412	0	3
T12	3888	3812	0	3
T13	3197	3126	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	955	955	0	0
OutputsKnown_A	24358090	23839177	0	0
gen_flops.OutputDelay_A	24358090	23818318	0	2865

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	23839177	0	0
T1	2164	2069	0	0
T2	1784	1391	0	0
T3	647834	639702	0	0
T7	4640	4571	0	0
T8	3237	3166	0	0
T9	1727	1652	0	0
T10	7211	6260	0	0
T11	54586	54418	0	0
T12	3888	3815	0	0
T13	3197	3129	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	23818318	0	2865
T1	2164	2066	0	3
T2	1784	1376	0	3
T3	647834	639372	0	3
T7	4640	4568	0	3
T8	3237	3163	0	3
T9	1727	1649	0	3
T10	7211	6221	0	3
T11	54586	54412	0	3
T12	3888	3812	0	3
T13	3197	3126	0	3