Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73074270	143026	0	0
StatusRise_A	73074270	159803	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73074270	143026	0	0
T1	6492	20	0	0
T2	5352	0	0	0
T3	1943502	2770	0	0
T7	13920	0	0	0
T8	9711	30	0	0
T9	5181	9	0	0
T10	21633	54	0	0
T11	163758	235	0	0
T12	11664	43	0	0
T13	9591	63	0	0
T22	0	21	0	0
T37	0	49	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73074270	159803	0	0
T1	6492	23	0	0
T2	5352	15	0	0
T3	1943502	3058	0	0
T7	13920	3	0	0
T8	9711	33	0	0
T9	5181	12	0	0
T10	21633	60	0	0
T11	163758	241	0	0
T12	11664	45	0	0
T13	9591	66	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24358090	53123	0	0
StatusRise_A	24358090	59171	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	53123	0	0
T1	2164	7	0	0
T2	1784	0	0	0
T3	647834	1036	0	0
T7	4640	0	0	0
T8	3237	13	0	0
T9	1727	3	0	0
T10	7211	18	0	0
T11	54586	90	0	0
T12	3888	16	0	0
T13	3197	21	0	0
T22	0	7	0	0
T37	0	19	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	59171	0	0
T1	2164	8	0	0
T2	1784	5	0	0
T3	647834	1144	0	0
T7	4640	1	0	0
T8	3237	14	0	0
T9	1727	4	0	0
T10	7211	20	0	0
T11	54586	92	0	0
T12	3888	17	0	0
T13	3197	22	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24358090	53123	0	0
StatusRise_A	24358090	59171	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	53123	0	0
T1	2164	7	0	0
T2	1784	0	0	0
T3	647834	1036	0	0
T7	4640	0	0	0
T8	3237	13	0	0
T9	1727	3	0	0
T10	7211	18	0	0
T11	54586	90	0	0
T12	3888	16	0	0
T13	3197	21	0	0
T22	0	7	0	0
T37	0	19	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	59171	0	0
T1	2164	8	0	0
T2	1784	5	0	0
T3	647834	1144	0	0
T7	4640	1	0	0
T8	3237	14	0	0
T9	1727	4	0	0
T10	7211	20	0	0
T11	54586	92	0	0
T12	3888	17	0	0
T13	3197	22	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24358090	36780	0	0
StatusRise_A	24358090	41461	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	36780	0	0
T1	2164	6	0	0
T2	1784	0	0	0
T3	647834	698	0	0
T7	4640	0	0	0
T8	3237	4	0	0
T9	1727	3	0	0
T10	7211	18	0	0
T11	54586	55	0	0
T12	3888	11	0	0
T13	3197	21	0	0
T22	0	7	0	0
T37	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	41461	0	0
T1	2164	7	0	0
T2	1784	5	0	0
T3	647834	770	0	0
T7	4640	1	0	0
T8	3237	5	0	0
T9	1727	4	0	0
T10	7211	20	0	0
T11	54586	57	0	0
T12	3888	11	0	0
T13	3197	22	0	0