Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24358681	6132	0	0
EscTimeoutStoppedByClReset_A	24358090	3438962	0	0
EscTimeoutTriggersReset_A	4825780	328	0	0
RomAllowActiveState_A	24358090	58782	0	0
RomAllowCheckGoodState_A	24358090	58832	0	0
RomBlockActiveState_A	24358090	30491	0	0
RomBlockCheckGoodState_A	24358090	401554	0	0
RomIntgChkDisFalse_A	24358090	23734243	0	0
RomIntgChkDisTrue_A	24358090	104934	0	0
RstreqChkEsctimeout_A	24358090	4357	0	0
RstreqChkFsmterm_A	24358090	120	0	0
RstreqChkGlbesc_A	24358090	4357	0	0
RstreqChkMainpd_A	24358090	1000611	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358681	6132	0	0
T14	15144	65	0	0
T15	838	5	0	0
T16	902	0	0	0
T32	0	43	0	0
T43	3142	0	0	0
T76	114353	0	0	0
T77	78714	0	0	0
T78	155938	0	0	0
T135	0	3	0	0
T139	0	54	0	0
T140	0	230	0	0
T141	0	56	0	0
T142	0	93	0	0
T143	0	181	0	0
T144	0	3	0	0
T145	28937	0	0	0
T146	30840	0	0	0
T147	5619	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	3438962	0	0
T1	2164	52	0	0
T2	1784	52	0	0
T3	647834	124207	0	0
T7	4640	1	0	0
T8	3237	640	0	0
T9	1727	44	0	0
T10	7211	505	0	0
T11	54586	12319	0	0
T12	3888	18	0	0
T13	3197	437	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4825780	328	0	0
T14	574	3	0	0
T15	266	3	0	0
T16	256	4	0	0
T32	0	3	0	0
T43	300	0	0	0
T76	13103	0	0	0
T77	14560	0	0	0
T78	56592	0	0	0
T135	0	5	0	0
T139	0	3	0	0
T140	0	3	0	0
T145	5678	0	0	0
T146	5855	0	0	0
T147	606	0	0	0
T148	0	2	0	0
T149	0	6	0	0
T150	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	58782	0	0
T1	2164	8	0	0
T2	1784	5	0	0
T3	647834	1143	0	0
T7	4640	1	0	0
T8	3237	14	0	0
T9	1727	4	0	0
T10	7211	13	0	0
T11	54586	92	0	0
T12	3888	17	0	0
T13	3197	22	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	58832	0	0
T1	2164	8	0	0
T2	1784	5	0	0
T3	647834	1143	0	0
T7	4640	1	0	0
T8	3237	14	0	0
T9	1727	4	0	0
T10	7211	14	0	0
T11	54586	92	0	0
T12	3888	17	0	0
T13	3197	22	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	30491	0	0
T17	223363	0	0	0
T22	4066	771	0	0
T23	22412	0	0	0
T24	2907	600	0	0
T27	0	258	0	0
T31	0	1109	0	0
T34	0	210	0	0
T36	16055	6	0	0
T38	2294	0	0	0
T41	1767	0	0	0
T53	8581	0	0	0
T74	6377	0	0	0
T75	6792	0	0	0
T125	0	6	0	0
T151	0	8	0	0
T152	0	1234	0	0
T153	0	1556	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	401554	0	0
T3	647834	4937	0	0
T7	4640	0	0	0
T8	3237	207	0	0
T9	1727	0	0	0
T10	7211	0	0	0
T11	54586	4079	0	0
T12	3888	0	0	0
T13	3197	0	0	0
T17	0	802	0	0
T21	0	2588	0	0
T22	4066	505	0	0
T23	0	1327	0	0
T24	0	242	0	0
T36	0	768	0	0
T37	11007	0	0	0
T72	0	391	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	23734243	0	0
T1	2164	2069	0	0
T2	1784	1391	0	0
T3	647834	639702	0	0
T7	4640	4571	0	0
T8	3237	3166	0	0
T9	1727	1652	0	0
T10	7211	6260	0	0
T11	54586	54418	0	0
T12	3888	3815	0	0
T13	3197	3129	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	104934	0	0
T17	223363	0	0	0
T22	4066	102	0	0
T23	22412	437	0	0
T24	2907	1119	0	0
T27	0	208	0	0
T31	0	295	0	0
T34	0	245	0	0
T36	16055	0	0	0
T38	2294	0	0	0
T41	1767	0	0	0
T53	8581	0	0	0
T74	6377	0	0	0
T75	6792	0	0	0
T151	0	317	0	0
T152	0	2346	0	0
T154	0	335	0	0
T155	0	3629	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	4357	0	0
T2	1784	4	0	0
T3	647834	64	0	0
T7	4640	0	0	0
T8	3237	0	0	0
T9	1727	0	0	0
T10	7211	4	0	0
T11	54586	0	0	0
T12	3888	0	0	0
T13	3197	15	0	0
T17	0	30	0	0
T21	0	21	0	0
T22	0	4	0	0
T24	0	5	0	0
T37	11007	0	0	0
T38	0	1	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	120	0	0
T4	23485	20	0	0
T5	0	20	0	0
T6	0	40	0	0
T25	0	20	0	0
T26	0	20	0	0
T27	2041	0	0	0
T28	1045	0	0	0
T29	1838	0	0	0
T30	46665	0	0	0
T31	4596	0	0	0
T32	14973	0	0	0
T33	1235	0	0	0
T34	1704	0	0	0
T35	5861	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	4357	0	0
T2	1784	4	0	0
T3	647834	64	0	0
T7	4640	0	0	0
T8	3237	0	0	0
T9	1727	0	0	0
T10	7211	4	0	0
T11	54586	0	0	0
T12	3888	0	0	0
T13	3197	15	0	0
T17	0	30	0	0
T21	0	21	0	0
T22	0	4	0	0
T24	0	5	0	0
T37	11007	0	0	0
T38	0	1	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24358090	1000611	0	0
T3	647834	26374	0	0
T7	4640	0	0	0
T8	3237	192	0	0
T9	1727	0	0	0
T10	7211	218	0	0
T11	54586	3574	0	0
T12	3888	0	0	0
T13	3197	247	0	0
T17	0	6467	0	0
T22	4066	542	0	0
T23	0	1411	0	0
T24	0	239	0	0
T36	0	1493	0	0
T37	11007	0	0	0