Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	524817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207261

1

T1

33

T2

23

T4

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	389838	1			T1	43		T2	31		T3	1
values[0x0]	170287	1			T1	35		T2	10		T4	14
values[0x1]	171953	1			T1	53		T2	6		T4	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	415982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

316096

1

T1

49

T2

27

T4

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3020	1			T4	1		T6	1		T10	13
valid_sources[0x01]	1901	1			T6	1		T10	24		T40	1
valid_sources[0x02]	5699	1			T4	1		T10	12		T40	2
valid_sources[0x03]	2118	1			T24	1		T37	6		T22	34
valid_sources[0x04]	2041	1			T6	7		T10	40		T24	1
valid_sources[0x05]	2027	1			T6	3		T37	3		T22	8
valid_sources[0x06]	4693	1			T6	6		T10	47		T40	1
valid_sources[0x07]	2032	1			T6	2		T25	1		T40	3
valid_sources[0x08]	2240	1			T4	1		T6	3		T10	271
valid_sources[0x09]	3731	1			T10	12		T37	2		T22	6
valid_sources[0x0a]	2767	1			T6	1		T37	3		T22	3
valid_sources[0x0b]	3017	1			T2	1		T10	12		T25	1
valid_sources[0x0c]	2882	1			T6	9		T10	24		T24	1
valid_sources[0x0d]	4572	1			T6	8		T41	3		T37	3
valid_sources[0x0e]	3441	1			T6	11		T10	12		T24	1
valid_sources[0x0f]	3268	1			T6	5		T10	13		T25	2
valid_sources[0x10]	3505	1			T10	1020		T25	2		T41	28
valid_sources[0x11]	3162	1			T1	12		T6	5		T10	142
valid_sources[0x12]	1824	1			T6	3		T37	3		T22	1
valid_sources[0x13]	2257	1			T6	3		T10	12		T37	4
valid_sources[0x14]	1992	1			T6	5		T40	1		T41	2
valid_sources[0x15]	3179	1			T2	1		T10	228		T37	3
valid_sources[0x16]	10058	1			T2	1		T6	5		T10	36
valid_sources[0x17]	2007	1			T6	1		T10	13		T41	7
valid_sources[0x18]	2307	1			T24	1		T37	1		T47	1
valid_sources[0x19]	2092	1			T6	2		T10	22		T79	4
valid_sources[0x1a]	2188	1			T10	1		T24	1		T37	3
valid_sources[0x1b]	2643	1			T4	3		T6	7		T10	168
valid_sources[0x1c]	1883	1			T6	3		T10	11		T40	1
valid_sources[0x1d]	2216	1			T1	13		T6	1		T10	12
valid_sources[0x1e]	2116	1			T6	1		T10	2		T41	8
valid_sources[0x1f]	2292	1			T10	13		T37	3		T22	1
valid_sources[0x20]	2357	1			T6	1		T10	22		T22	1
valid_sources[0x21]	3487	1			T6	2		T41	8		T37	5
valid_sources[0x22]	2104	1			T6	4		T40	1		T37	6
valid_sources[0x23]	2352	1			T6	7		T10	22		T37	3
valid_sources[0x24]	2893	1			T6	7		T10	25		T37	5
valid_sources[0x25]	3624	1			T6	6		T10	11		T37	5
valid_sources[0x26]	2756	1			T1	12		T6	5		T41	4
valid_sources[0x27]	1932	1			T10	24		T37	3		T38	3
valid_sources[0x28]	2106	1			T6	1		T37	5		T38	1
valid_sources[0x29]	1738	1			T6	6		T10	13		T40	1
valid_sources[0x2a]	2257	1			T10	12		T37	2		T22	1
valid_sources[0x2b]	3697	1			T7	4		T10	830		T25	2
valid_sources[0x2c]	15281	1			T10	12		T24	1		T176	1
valid_sources[0x2d]	3025	1			T10	12		T37	2		T22	7
valid_sources[0x2e]	2078	1			T6	6		T10	12		T24	1
valid_sources[0x2f]	2045	1			T6	1		T37	2		T22	6
valid_sources[0x30]	2463	1			T10	24		T37	7		T79	1
valid_sources[0x31]	3083	1			T37	1		T22	4		T176	1
valid_sources[0x32]	1941	1			T6	3		T23	1		T83	1
valid_sources[0x33]	1845	1			T6	8		T41	2		T37	4
valid_sources[0x34]	3547	1			T6	10		T9	859		T25	5
valid_sources[0x35]	3972	1			T4	1		T10	24		T41	4
valid_sources[0x36]	3524	1			T10	12		T41	7		T37	2
valid_sources[0x37]	2073	1			T10	2		T25	1		T83	1
valid_sources[0x38]	2594	1			T6	2		T10	1		T37	7
valid_sources[0x39]	3176	1			T4	1		T10	14		T37	1
valid_sources[0x3a]	2300	1			T6	8		T37	5		T22	4
valid_sources[0x3b]	2142	1			T6	3		T10	22		T24	2
valid_sources[0x3c]	1917	1			T6	1		T10	12		T37	4
valid_sources[0x3d]	4130	1			T6	4		T10	7		T37	2
valid_sources[0x3e]	4581	1			T4	1		T6	1		T10	12
valid_sources[0x3f]	2259	1			T6	2		T10	1		T37	3
valid_sources[0x40]	4618	1			T4	2		T6	4		T37	7
valid_sources[0x41]	2384	1			T6	1		T10	26		T37	4
valid_sources[0x42]	11913	1			T6	6		T10	12		T41	3
valid_sources[0x43]	1944	1			T41	3		T24	1		T37	6
valid_sources[0x44]	3341	1			T6	5		T10	1314		T37	3
valid_sources[0x45]	4048	1			T4	1		T25	1		T41	1
valid_sources[0x46]	2158	1			T10	13		T41	2		T37	2
valid_sources[0x47]	3234	1			T10	25		T41	10		T24	1
valid_sources[0x48]	3786	1			T10	12		T37	3		T23	1
valid_sources[0x49]	2199	1			T6	1		T10	22		T25	2
valid_sources[0x4a]	4357	1			T6	3		T10	23		T37	1
valid_sources[0x4b]	3009	1			T6	2		T10	14		T41	6
valid_sources[0x4c]	2133	1			T6	4		T37	4		T178	1
valid_sources[0x4d]	2224	1			T6	2		T25	2		T37	1
valid_sources[0x4e]	2409	1			T2	1		T6	9		T37	1
valid_sources[0x4f]	2214	1			T6	4		T24	1		T37	5
valid_sources[0x50]	2113	1			T6	3		T10	13		T37	6
valid_sources[0x51]	2546	1			T6	9		T10	528		T40	1
valid_sources[0x52]	6175	1			T10	12		T37	3		T129	1
valid_sources[0x53]	2685	1			T6	6		T10	12		T37	1
valid_sources[0x54]	2377	1			T2	1		T4	1		T6	3
valid_sources[0x55]	2014	1			T4	1		T176	2		T79	1
valid_sources[0x56]	2207	1			T6	6		T10	24		T25	3
valid_sources[0x57]	2272	1			T10	303		T79	2		T47	1
valid_sources[0x58]	4027	1			T6	1		T24	1		T37	2
valid_sources[0x59]	2360	1			T6	2		T10	12		T37	1
valid_sources[0x5a]	2674	1			T6	6		T37	5		T22	1
valid_sources[0x5b]	2310	1			T37	4		T39	17		T13	13
valid_sources[0x5c]	3821	1			T6	3		T10	968		T40	1
valid_sources[0x5d]	2450	1			T41	9		T37	6		T176	2
valid_sources[0x5e]	4688	1			T6	5		T10	26		T37	3
valid_sources[0x5f]	3130	1			T1	12		T6	4		T10	13
valid_sources[0x60]	2844	1			T6	13		T10	12		T37	1
valid_sources[0x61]	3367	1			T10	12		T40	2		T37	3
valid_sources[0x62]	2283	1			T4	1		T6	2		T10	14
valid_sources[0x63]	8607	1			T2	2		T4	2		T6	1
valid_sources[0x64]	2169	1			T6	6		T10	13		T37	2
valid_sources[0x65]	2885	1			T6	11		T10	12		T41	4
valid_sources[0x66]	2204	1			T6	8		T10	15		T41	8
valid_sources[0x67]	2210	1			T10	12		T37	5		T176	2
valid_sources[0x68]	2092	1			T4	2		T6	9		T10	12
valid_sources[0x69]	2658	1			T6	8		T10	12		T25	2
valid_sources[0x6a]	2072	1			T2	1		T4	2		T6	2
valid_sources[0x6b]	1989	1			T6	1		T10	12		T37	2
valid_sources[0x6c]	2192	1			T6	2		T25	1		T41	2
valid_sources[0x6d]	2586	1			T6	7		T10	23		T41	4
valid_sources[0x6e]	2348	1			T6	8		T10	11		T37	11
valid_sources[0x6f]	3352	1			T6	1		T10	12		T25	1
valid_sources[0x70]	2604	1			T10	338		T41	1		T37	3
valid_sources[0x71]	4685	1			T6	1		T10	12		T25	3
valid_sources[0x72]	2020	1			T1	11		T2	2		T6	6
valid_sources[0x73]	2003	1			T25	1		T178	2		T13	7
valid_sources[0x74]	2951	1			T6	1		T37	7		T22	1
valid_sources[0x75]	2179	1			T1	11		T37	3		T22	22
valid_sources[0x76]	2170	1			T10	13		T37	4		T79	1
valid_sources[0x77]	1933	1			T6	4		T37	5		T13	16
valid_sources[0x78]	2643	1			T2	1		T6	2		T37	1
valid_sources[0x79]	2406	1			T6	10		T10	12		T37	2
valid_sources[0x7a]	2361	1			T4	1		T6	2		T10	1
valid_sources[0x7b]	3507	1			T4	1		T6	7		T24	1
valid_sources[0x7c]	2283	1			T6	5		T10	13		T37	2
valid_sources[0x7d]	2217	1			T6	3		T10	12		T25	3
valid_sources[0x7e]	2079	1			T4	2		T6	7		T37	2
valid_sources[0x7f]	1987	1			T37	5		T23	1		T83	2
valid_sources[0x80]	4044	1			T10	1218		T41	10		T37	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

108607

1

T1

11

T2

14

T4

8

values[0x0]

all_enables

biggest_size

63651

1

T1

10

T2

6

T4

4

values[0x1]

all_enables

biggest_size

35003

1

T1

12

T2

3

T4

1