SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35192 | 1 | T9 | 292 | T37 | 407 | T22 | 321 | ||||
others[1] | 35025 | 1 | T9 | 293 | T24 | 2 | T37 | 396 | ||||
others[2] | 34847 | 1 | T9 | 281 | T24 | 1 | T37 | 416 | ||||
others[3] | 58203 | 1 | T9 | 520 | T37 | 670 | T22 | 467 | ||||
false | 18939 | 1 | T6 | 22 | T9 | 50 | T10 | 390 | ||||
true | 29163 | 1 | T1 | 1 | T2 | 5 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34841 | 1 | T9 | 330 | T24 | 1 | T37 | 411 | ||||
others[1] | 35172 | 1 | T9 | 293 | T37 | 370 | T22 | 278 | ||||
others[2] | 35037 | 1 | T9 | 295 | T24 | 1 | T37 | 385 | ||||
others[3] | 58585 | 1 | T9 | 484 | T37 | 695 | T22 | 523 | ||||
false | 12081 | 1 | T6 | 11 | T9 | 50 | T10 | 195 | ||||
true | 22361 | 1 | T1 | 1 | T2 | 5 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 698 | 1 | T10 | 15 | T25 | 1 | T13 | 8 | ||||
others[1] | 670 | 1 | T6 | 1 | T10 | 20 | T13 | 4 | ||||
others[2] | 681 | 1 | T6 | 2 | T10 | 5 | T25 | 1 | ||||
others[3] | 1122 | 1 | T6 | 4 | T10 | 18 | T25 | 2 | ||||
false | 13645 | 1 | T1 | 1 | T2 | 5 | T3 | 2 | ||||
true | 3905 | 1 | T6 | 4 | T10 | 89 | T25 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |