Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28146675	14359	0	0
intr_enable_rd_A	28146675	45280	0	0
reset_en_rd_A	28146675	1079	0	0
reset_en_regwen_rd_A	28146675	1024	0	0
wake_info_capture_dis_rd_A	28146675	1043	0	0
wakeup_en_rd_A	28146675	1523	0	0
wakeup_en_regwen_rd_A	28146675	1056	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	14359	0	0
T10	376228	9	0	0
T11	2472	0	0	0
T20	0	4	0	0
T21	0	12	0	0
T24	5930	0	0	0
T25	2968	0	0	0
T37	57462	0	0	0
T40	3121	0	0	0
T41	7256	0	0	0
T42	3176	0	0	0
T51	0	130	0	0
T52	0	43	0	0
T59	4168	0	0	0
T84	0	51	0	0
T124	0	1	0	0
T125	0	48	0	0
T126	0	54	0	0
T127	0	4	0	0
T128	1701	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	45280	0	0
T1	2232	21	0	0
T2	2132	0	0	0
T3	2286	0	0	0
T4	1634	0	0	0
T5	1656	0	0	0
T6	23836	0	0	0
T7	1019	0	0	0
T8	1018	0	0	0
T9	56804	176	0	0
T10	376228	0	0	0
T13	0	776	0	0
T22	0	99	0	0
T24	0	6	0	0
T40	0	12	0	0
T82	0	14	0	0
T129	0	31	0	0
T130	0	18	0	0
T131	0	93	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	1079	0	0
T20	153681	9	0	0
T55	0	1	0	0
T57	0	39	0	0
T69	0	13	0	0
T75	0	7	0	0
T102	0	16	0	0
T132	0	23	0	0
T133	0	8	0	0
T134	0	4	0	0
T135	0	3	0	0
T136	6775	0	0	0
T137	15028	0	0	0
T138	6814	0	0	0
T139	2468	0	0	0
T140	1514	0	0	0
T141	2285	0	0	0
T142	7431	0	0	0
T143	906	0	0	0
T144	1648	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	1024	0	0
T20	153681	2	0	0
T55	0	9	0	0
T57	0	42	0	0
T69	0	11	0	0
T75	0	2	0	0
T85	0	5	0	0
T102	0	17	0	0
T132	0	8	0	0
T136	6775	0	0	0
T137	15028	0	0	0
T138	6814	0	0	0
T139	2468	0	0	0
T140	1514	0	0	0
T141	2285	0	0	0
T142	7431	0	0	0
T143	906	0	0	0
T144	1648	0	0	0
T145	0	6	0	0
T146	0	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	1043	0	0
T20	153681	7	0	0
T55	0	1	0	0
T69	0	14	0	0
T75	0	5	0	0
T132	0	16	0	0
T133	0	14	0	0
T134	0	3	0	0
T135	0	6	0	0
T136	6775	0	0	0
T137	15028	0	0	0
T138	6814	0	0	0
T139	2468	0	0	0
T140	1514	0	0	0
T141	2285	0	0	0
T142	7431	0	0	0
T143	906	0	0	0
T144	1648	0	0	0
T145	0	5	0	0
T146	0	15	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	1523	0	0
T69	0	9	0	0
T75	0	11	0	0
T102	0	6	0	0
T132	474417	17	0	0
T133	0	1	0	0
T134	0	7	0	0
T135	0	11	0	0
T145	0	6	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	15008	0	0	0
T149	1323	0	0	0
T150	1307	0	0	0
T151	2567	0	0	0
T152	10743	0	0	0
T153	4773	0	0	0
T154	3050	0	0	0
T155	6425	0	0	0
T156	14789	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28146675	1056	0	0
T55	643160	2	0	0
T57	0	34	0	0
T69	0	22	0	0
T132	0	32	0	0
T133	0	8	0	0
T134	0	8	0	0
T135	0	6	0	0
T146	0	6	0	0
T147	0	5	0	0
T157	0	12	0	0
T158	19734	0	0	0
T159	1368	0	0	0
T160	2351	0	0	0
T161	6665	0	0	0
T162	5213	0	0	0
T163	15508	0	0	0
T164	1537	0	0	0
T165	57781	0	0	0
T166	1476	0	0	0