Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_dft_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_hw_debug_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1908	1908	0	0
OutputsKnown_A	55191926	54116864	0	0
gen_flops.OutputDelay_A	55191926	54073628	0	5724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1908	1908	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55191926	54116864	0	0
T1	4464	4300	0	0
T2	4264	3520	0	0
T3	4572	4270	0	0
T4	3268	3142	0	0
T5	3312	2586	0	0
T6	47672	46410	0	0
T7	2038	1892	0	0
T8	2036	1838	0	0
T9	113608	113494	0	0
T10	752456	732484	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55191926	54073628	0	5724
T1	4464	4294	0	6
T2	4264	3490	0	6
T3	4572	4258	0	6
T4	3268	3136	0	6
T5	3312	2556	0	6
T6	47672	46356	0	6
T7	2038	1886	0	6
T8	2036	1832	0	6
T9	113608	113488	0	6
T10	752456	731692	0	6

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	954	954	0	0
OutputsKnown_A	27595963	27058432	0	0
gen_flops.OutputDelay_A	27595963	27036814	0	2862

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	27058432	0	0
T1	2232	2150	0	0
T2	2132	1760	0	0
T3	2286	2135	0	0
T4	1634	1571	0	0
T5	1656	1293	0	0
T6	23836	23205	0	0
T7	1019	946	0	0
T8	1018	919	0	0
T9	56804	56747	0	0
T10	376228	366242	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	27036814	0	2862
T1	2232	2147	0	3
T2	2132	1745	0	3
T3	2286	2129	0	3
T4	1634	1568	0	3
T5	1656	1278	0	3
T6	23836	23178	0	3
T7	1019	943	0	3
T8	1018	916	0	3
T9	56804	56744	0	3
T10	376228	365846	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	954	954	0	0
OutputsKnown_A	27595963	27058432	0	0
gen_flops.OutputDelay_A	27595963	27036814	0	2862

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	27058432	0	0
T1	2232	2150	0	0
T2	2132	1760	0	0
T3	2286	2135	0	0
T4	1634	1571	0	0
T5	1656	1293	0	0
T6	23836	23205	0	0
T7	1019	946	0	0
T8	1018	919	0	0
T9	56804	56747	0	0
T10	376228	366242	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	27036814	0	2862
T1	2232	2147	0	3
T2	2132	1745	0	3
T3	2286	2129	0	3
T4	1634	1568	0	3
T5	1656	1278	0	3
T6	23836	23178	0	3
T7	1019	943	0	3
T8	1018	916	0	3
T9	56804	56744	0	3
T10	376228	365846	0	3