Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	82787889	148133	0	0
StatusRise_A	82787889	165286	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82787889	148133	0	0
T1	6696	33	0	0
T2	6396	12	0	0
T3	6858	3	0	0
T4	4902	10	0	0
T5	4968	0	0	0
T6	71508	185	0	0
T7	3057	6	0	0
T8	3054	6	0	0
T9	170412	206	0	0
T10	1128684	3316	0	0
T25	0	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82787889	165286	0	0
T1	6696	36	0	0
T2	6396	15	0	0
T3	6858	9	0	0
T4	4902	13	0	0
T5	4968	15	0	0
T6	71508	210	0	0
T7	3057	9	0	0
T8	3054	9	0	0
T9	170412	209	0	0
T10	1128684	3669	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	27595963	55038	0	0
StatusRise_A	27595963	61247	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	55038	0	0
T1	2232	11	0	0
T2	2132	4	0	0
T3	2286	1	0	0
T4	1634	4	0	0
T5	1656	0	0	0
T6	23836	71	0	0
T7	1019	2	0	0
T8	1018	2	0	0
T9	56804	83	0	0
T10	376228	1224	0	0
T25	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	61247	0	0
T1	2232	12	0	0
T2	2132	5	0	0
T3	2286	3	0	0
T4	1634	5	0	0
T5	1656	5	0	0
T6	23836	80	0	0
T7	1019	3	0	0
T8	1018	3	0	0
T9	56804	84	0	0
T10	376228	1356	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	27595963	55038	0	0
StatusRise_A	27595963	61249	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	55038	0	0
T1	2232	11	0	0
T2	2132	4	0	0
T3	2286	1	0	0
T4	1634	4	0	0
T5	1656	0	0	0
T6	23836	71	0	0
T7	1019	2	0	0
T8	1018	2	0	0
T9	56804	83	0	0
T10	376228	1224	0	0
T25	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	61249	0	0
T1	2232	12	0	0
T2	2132	5	0	0
T3	2286	3	0	0
T4	1634	5	0	0
T5	1656	5	0	0
T6	23836	80	0	0
T7	1019	3	0	0
T8	1018	3	0	0
T9	56804	84	0	0
T10	376228	1356	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	27595963	38057	0	0
StatusRise_A	27595963	42790	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	38057	0	0
T1	2232	11	0	0
T2	2132	4	0	0
T3	2286	1	0	0
T4	1634	2	0	0
T5	1656	0	0	0
T6	23836	43	0	0
T7	1019	2	0	0
T8	1018	2	0	0
T9	56804	40	0	0
T10	376228	868	0	0
T25	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	42790	0	0
T1	2232	12	0	0
T2	2132	5	0	0
T3	2286	3	0	0
T4	1634	3	0	0
T5	1656	5	0	0
T6	23836	50	0	0
T7	1019	3	0	0
T8	1018	3	0	0
T9	56804	41	0	0
T10	376228	957	0	0