Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	27596575	4961	0	0
EscTimeoutStoppedByClReset_A	27595963	3992968	0	0
EscTimeoutTriggersReset_A	4739275	308	0	0
RomAllowActiveState_A	27595963	60820	0	0
RomAllowCheckGoodState_A	27595963	60872	0	0
RomBlockActiveState_A	27595963	29503	0	0
RomBlockCheckGoodState_A	27595963	433937	0	0
RomIntgChkDisFalse_A	27595963	26777107	0	0
RomIntgChkDisTrue_A	27595963	281325	0	0
RstreqChkEsctimeout_A	27595963	4252	0	0
RstreqChkFsmterm_A	27595963	200	0	0
RstreqChkGlbesc_A	27595963	4252	0	0
RstreqChkMainpd_A	27595963	1147454	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27596575	4961	0	0
T12	15205	30	0	0
T23	5410	0	0	0
T43	5391	0	0	0
T79	2378	0	0	0
T80	6589	0	0	0
T81	6053	0	0	0
T137	0	3	0	0
T168	0	50	0	0
T169	0	55	0	0
T170	0	2	0	0
T171	0	55	0	0
T172	0	144	0	0
T173	0	29	0	0
T174	0	4	0	0
T175	0	19	0	0
T176	5368	0	0	0
T177	1730	0	0	0
T178	5031	0	0	0
T179	1733	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	3992968	0	0
T2	2132	61	0	0
T3	2286	10	0	0
T4	1634	101	0	0
T5	1656	21	0	0
T6	23836	2759	0	0
T7	1019	22	0	0
T8	1018	11	0	0
T9	56804	10195	0	0
T10	376228	40347	0	0
T25	2968	295	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4739275	308	0	0
T3	199	2	0	0
T4	1773	0	0	0
T5	2010	0	0	0
T6	8644	0	0	0
T7	335	0	0	0
T8	333	0	0	0
T9	5755	0	0	0
T10	130629	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T25	1065	0	0	0
T40	522	0	0	0
T137	0	3	0	0
T168	0	3	0	0
T169	0	3	0	0
T170	0	2	0	0
T171	0	3	0	0
T180	0	2	0	0
T181	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	60820	0	0
T1	2232	12	0	0
T2	2132	5	0	0
T3	2286	3	0	0
T4	1634	5	0	0
T5	1656	5	0	0
T6	23836	80	0	0
T7	1019	3	0	0
T8	1018	3	0	0
T9	56804	84	0	0
T10	376228	1356	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	60872	0	0
T1	2232	12	0	0
T2	2132	5	0	0
T3	2286	3	0	0
T4	1634	5	0	0
T5	1656	5	0	0
T6	23836	80	0	0
T7	1019	3	0	0
T8	1018	3	0	0
T9	56804	84	0	0
T10	376228	1356	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	29503	0	0
T11	2472	0	0	0
T12	15204	0	0	0
T22	17236	1	0	0
T23	0	1196	0	0
T24	5930	1134	0	0
T37	57462	0	0	0
T38	4729	0	0	0
T39	3097	0	0	0
T42	3176	0	0	0
T43	0	1015	0	0
T59	4168	0	0	0
T128	1701	0	0	0
T141	0	235	0	0
T176	0	1436	0	0
T182	0	11	0	0
T183	0	1	0	0
T184	0	34	0	0
T185	0	300	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	433937	0	0
T6	23836	253	0	0
T7	1019	0	0	0
T8	1018	0	0	0
T9	56804	4109	0	0
T10	376228	4477	0	0
T11	2472	0	0	0
T22	0	717	0	0
T23	0	1047	0	0
T24	5930	880	0	0
T25	2968	0	0	0
T37	0	4131	0	0
T40	3121	0	0	0
T41	7256	0	0	0
T43	0	549	0	0
T79	0	114	0	0
T176	0	869	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	26777107	0	0
T1	2232	2150	0	0
T2	2132	1760	0	0
T3	2286	2135	0	0
T4	1634	1571	0	0
T5	1656	1293	0	0
T6	23836	23205	0	0
T7	1019	946	0	0
T8	1018	919	0	0
T9	56804	53674	0	0
T10	376228	366242	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	281325	0	0
T9	56804	3073	0	0
T10	376228	0	0	0
T11	2472	0	0	0
T22	0	18	0	0
T23	0	1926	0	0
T24	5930	0	0	0
T25	2968	0	0	0
T37	57462	0	0	0
T40	3121	0	0	0
T41	7256	0	0	0
T42	3176	0	0	0
T128	1701	0	0	0
T141	0	1163	0	0
T176	0	1358	0	0
T184	0	153	0	0
T185	0	181	0	0
T186	0	223	0	0
T187	0	906	0	0
T188	0	894	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	4252	0	0
T3	2286	1	0	0
T4	1634	0	0	0
T5	1656	4	0	0
T6	23836	13	0	0
T7	1019	0	0	0
T8	1018	0	0	0
T9	56804	0	0	0
T10	376228	93	0	0
T11	0	1	0	0
T24	0	5	0	0
T25	2968	3	0	0
T38	0	9	0	0
T39	0	7	0	0
T40	3121	0	0	0
T42	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	200	0	0
T17	17332	40	0	0
T18	0	40	0	0
T19	0	40	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	530043	0	0	0
T29	28895	0	0	0
T30	1135	0	0	0
T31	250760	0	0	0
T32	15199	0	0	0
T33	15860	0	0	0
T34	9327	0	0	0
T35	16375	0	0	0
T36	4893	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	4252	0	0
T3	2286	1	0	0
T4	1634	0	0	0
T5	1656	4	0	0
T6	23836	13	0	0
T7	1019	0	0	0
T8	1018	0	0	0
T9	56804	0	0	0
T10	376228	93	0	0
T11	0	1	0	0
T24	0	5	0	0
T25	2968	3	0	0
T38	0	9	0	0
T39	0	7	0	0
T40	3121	0	0	0
T42	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27595963	1147454	0	0
T6	23836	395	0	0
T7	1019	0	0	0
T8	1018	0	0	0
T9	56804	6714	0	0
T10	376228	9751	0	0
T11	2472	0	0	0
T22	0	872	0	0
T23	0	301	0	0
T24	5930	1000	0	0
T25	2968	84	0	0
T37	0	6599	0	0
T38	0	225	0	0
T39	0	578	0	0
T40	3121	0	0	0
T41	7256	0	0	0