Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

192132

1

T1

203

T2

8

T3

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	362493	1			T1	408		T2	39		T3	93
values[0x0]	170821	1			T1	219		T2	10		T3	55
values[0x1]	171176	1			T1	233		T2	12		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

298684

1

T1

342

T2

16

T3

78

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3693	1			T1	1		T4	4		T8	1
valid_sources[0x01]	2146	1			T1	6		T2	8		T4	13
valid_sources[0x02]	2084	1			T1	2		T4	2		T10	1
valid_sources[0x03]	2220	1			T4	1		T7	3		T10	4
valid_sources[0x04]	2334	1			T4	8		T7	5		T10	3
valid_sources[0x05]	2065	1			T1	6		T4	4		T26	1
valid_sources[0x06]	2531	1			T1	2		T4	14		T7	1
valid_sources[0x07]	2328	1			T1	1		T4	16		T7	1
valid_sources[0x08]	2160	1			T1	2		T4	7		T7	1
valid_sources[0x09]	3095	1			T4	7		T5	1		T10	1
valid_sources[0x0a]	3122	1			T1	6		T7	3		T10	2
valid_sources[0x0b]	3985	1			T1	1		T4	12		T7	1
valid_sources[0x0c]	3757	1			T4	10		T13	1		T26	5
valid_sources[0x0d]	2100	1			T1	3		T4	10		T10	4
valid_sources[0x0e]	2469	1			T1	3		T4	3		T7	4
valid_sources[0x0f]	2289	1			T1	6		T4	7		T10	1
valid_sources[0x10]	2339	1			T1	2		T4	1		T10	2
valid_sources[0x11]	2561	1			T1	3		T4	3		T13	1
valid_sources[0x12]	2153	1			T1	8		T4	1		T7	1
valid_sources[0x13]	3416	1			T1	3		T4	3		T7	2
valid_sources[0x14]	3516	1			T1	2		T4	9		T10	4
valid_sources[0x15]	2709	1			T1	4		T4	6		T7	3
valid_sources[0x16]	2733	1			T1	7		T4	2		T10	1
valid_sources[0x17]	2359	1			T1	1		T4	13		T10	1
valid_sources[0x18]	2253	1			T1	1		T4	10		T13	1
valid_sources[0x19]	2230	1			T1	2		T4	6		T8	3
valid_sources[0x1a]	3222	1			T1	1		T4	11		T10	6
valid_sources[0x1b]	4139	1			T1	3		T2	3		T4	8
valid_sources[0x1c]	2377	1			T1	5		T4	2		T7	7
valid_sources[0x1d]	2571	1			T1	6		T4	28		T7	2
valid_sources[0x1e]	2308	1			T4	10		T10	4		T13	4
valid_sources[0x1f]	5211	1			T1	1		T8	4		T10	2
valid_sources[0x20]	3371	1			T1	2		T4	7		T10	3
valid_sources[0x21]	3122	1			T1	2		T4	10		T7	2
valid_sources[0x22]	2153	1			T1	2		T4	3		T13	2
valid_sources[0x23]	2165	1			T1	6		T7	1		T10	4
valid_sources[0x24]	2897	1			T1	1		T4	4		T10	8
valid_sources[0x25]	3452	1			T1	3		T4	1		T7	3
valid_sources[0x26]	2162	1			T1	1		T4	3		T26	4
valid_sources[0x27]	3742	1			T1	4		T4	5		T6	125
valid_sources[0x28]	2621	1			T1	5		T4	9		T13	1
valid_sources[0x29]	2854	1			T1	5		T2	7		T4	7
valid_sources[0x2a]	2176	1			T1	1		T4	5		T26	1
valid_sources[0x2b]	2000	1			T1	2		T4	11		T26	4
valid_sources[0x2c]	2579	1			T1	4		T4	12		T10	7
valid_sources[0x2d]	2587	1			T1	10		T4	1		T7	4
valid_sources[0x2e]	3865	1			T1	3		T4	5		T10	5
valid_sources[0x2f]	2332	1			T1	1		T4	13		T8	2
valid_sources[0x30]	2168	1			T1	2		T4	6		T7	2
valid_sources[0x31]	2273	1			T1	5		T4	12		T7	1
valid_sources[0x32]	2878	1			T1	3		T4	7		T7	1
valid_sources[0x33]	2415	1			T1	1		T4	1		T10	1
valid_sources[0x34]	2631	1			T1	2		T4	1		T7	1
valid_sources[0x35]	2506	1			T1	5		T4	10		T13	1
valid_sources[0x36]	2242	1			T1	2		T4	3		T7	2
valid_sources[0x37]	3181	1			T1	1		T4	14		T13	1
valid_sources[0x38]	2481	1			T1	8		T4	1		T7	1
valid_sources[0x39]	2461	1			T1	4		T4	12		T7	1
valid_sources[0x3a]	2407	1			T1	3		T7	1		T10	4
valid_sources[0x3b]	2997	1			T1	2		T4	6		T10	3
valid_sources[0x3c]	2385	1			T1	3		T4	2		T13	1
valid_sources[0x3d]	2718	1			T4	2		T7	1		T10	2
valid_sources[0x3e]	3343	1			T1	4		T3	197		T4	5
valid_sources[0x3f]	3276	1			T1	5		T4	16		T7	2
valid_sources[0x40]	3496	1			T1	2		T4	4		T7	2
valid_sources[0x41]	2431	1			T1	3		T4	11		T7	4
valid_sources[0x42]	2147	1			T1	3		T4	4		T8	1
valid_sources[0x43]	2327	1			T1	1		T4	5		T13	3
valid_sources[0x44]	4176	1			T1	2		T4	10		T10	1
valid_sources[0x45]	2161	1			T1	5		T10	1		T26	5
valid_sources[0x46]	1929	1			T1	3		T4	8		T7	3
valid_sources[0x47]	2369	1			T1	1		T4	23		T10	11
valid_sources[0x48]	2758	1			T1	2		T7	9		T10	2
valid_sources[0x49]	2747	1			T1	2		T4	9		T10	4
valid_sources[0x4a]	2241	1			T1	1		T4	8		T13	2
valid_sources[0x4b]	1959	1			T1	6		T4	9		T10	1
valid_sources[0x4c]	3269	1			T1	2		T4	5		T7	2
valid_sources[0x4d]	2029	1			T4	3		T7	2		T10	1
valid_sources[0x4e]	3596	1			T1	2		T2	5		T4	5
valid_sources[0x4f]	2795	1			T1	2		T4	2		T7	2
valid_sources[0x50]	5325	1			T1	3		T4	8		T7	3
valid_sources[0x51]	1966	1			T1	5		T4	9		T7	3
valid_sources[0x52]	3081	1			T1	1		T4	1		T26	4
valid_sources[0x53]	2388	1			T1	3		T7	2		T10	1
valid_sources[0x54]	3247	1			T1	1		T4	12		T10	2
valid_sources[0x55]	2261	1			T1	2		T4	8		T10	3
valid_sources[0x56]	3319	1			T1	7		T4	10		T10	1
valid_sources[0x57]	2612	1			T1	2		T4	1		T7	5
valid_sources[0x58]	2360	1			T1	1		T4	7		T10	4
valid_sources[0x59]	2314	1			T1	4		T4	10		T7	1
valid_sources[0x5a]	2652	1			T1	10		T4	11		T7	3
valid_sources[0x5b]	2167	1			T1	2		T4	7		T13	1
valid_sources[0x5c]	2453	1			T1	1		T4	4		T7	4
valid_sources[0x5d]	2315	1			T1	8		T4	7		T10	2
valid_sources[0x5e]	2064	1			T1	2		T4	8		T7	5
valid_sources[0x5f]	5528	1			T4	15		T26	2		T32	5
valid_sources[0x60]	3155	1			T1	1		T4	21		T26	4
valid_sources[0x61]	2176	1			T1	1		T4	19		T7	1
valid_sources[0x62]	2334	1			T1	10		T4	4		T7	6
valid_sources[0x63]	2024	1			T1	3		T26	5		T32	1
valid_sources[0x64]	2156	1			T1	10		T4	2		T7	1
valid_sources[0x65]	4625	1			T1	4		T4	4		T26	4
valid_sources[0x66]	2523	1			T1	2		T4	2		T10	1
valid_sources[0x67]	2191	1			T1	1		T4	3		T7	1
valid_sources[0x68]	2406	1			T1	2		T4	6		T10	2
valid_sources[0x69]	3812	1			T1	3		T4	7		T10	3
valid_sources[0x6a]	3152	1			T1	6		T4	6		T13	1
valid_sources[0x6b]	2237	1			T1	5		T4	1		T7	2
valid_sources[0x6c]	1864	1			T1	6		T4	13		T8	2
valid_sources[0x6d]	2553	1			T1	2		T4	2		T7	4
valid_sources[0x6e]	2949	1			T1	8		T4	9		T7	1
valid_sources[0x6f]	3849	1			T2	7		T4	18		T25	1
valid_sources[0x70]	2192	1			T1	1		T4	20		T25	2
valid_sources[0x71]	2089	1			T1	4		T4	3		T7	1
valid_sources[0x72]	3064	1			T1	3		T2	4		T4	5
valid_sources[0x73]	2075	1			T4	3		T7	3		T10	2
valid_sources[0x74]	2041	1			T1	1		T4	5		T10	1
valid_sources[0x75]	2381	1			T1	3		T4	3		T13	1
valid_sources[0x76]	2082	1			T4	1		T7	5		T13	4
valid_sources[0x77]	2985	1			T1	7		T4	11		T7	4
valid_sources[0x78]	2372	1			T1	6		T4	5		T13	2
valid_sources[0x79]	3380	1			T1	11		T4	6		T10	1
valid_sources[0x7a]	2537	1			T1	5		T4	2		T7	11
valid_sources[0x7b]	2352	1			T1	4		T4	3		T7	7
valid_sources[0x7c]	2039	1			T1	1		T4	4		T13	1
valid_sources[0x7d]	3062	1			T1	4		T4	5		T7	2
valid_sources[0x7e]	2936	1			T4	4		T10	5		T13	1
valid_sources[0x7f]	2163	1			T1	4		T4	7		T7	2
valid_sources[0x80]	2696	1			T1	2		T4	7		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

94627

1

T1

90

T2

4

T3

21

values[0x0]

all_enables

biggest_size

63241

1

T1

73

T2

3

T3

22

values[0x1]

all_enables

biggest_size

34264

1

T1

40

T2

1

T3

12