SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34976 | 1 | T1 | 393 | T2 | 1 | T26 | 309 | ||||
others[1] | 35108 | 1 | T1 | 412 | T2 | 1 | T26 | 290 | ||||
others[2] | 35093 | 1 | T1 | 431 | T26 | 284 | T32 | 409 | ||||
others[3] | 58273 | 1 | T1 | 638 | T2 | 1 | T26 | 524 | ||||
false | 19262 | 1 | T1 | 50 | T2 | 2 | T4 | 50 | ||||
true | 29345 | 1 | T1 | 102 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35112 | 1 | T1 | 413 | T2 | 1 | T25 | 2 | ||||
others[1] | 34728 | 1 | T1 | 403 | T26 | 297 | T32 | 408 | ||||
others[2] | 34932 | 1 | T1 | 370 | T26 | 289 | T32 | 384 | ||||
others[3] | 58560 | 1 | T1 | 670 | T26 | 503 | T32 | 682 | ||||
false | 12229 | 1 | T1 | 50 | T2 | 3 | T4 | 25 | ||||
true | 22375 | 1 | T1 | 102 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 716 | 1 | T2 | 1 | T29 | 7 | T34 | 1 | ||||
others[1] | 712 | 1 | T4 | 2 | T25 | 1 | T29 | 5 | ||||
others[2] | 704 | 1 | T2 | 2 | T4 | 1 | T29 | 5 | ||||
others[3] | 1068 | 1 | T4 | 1 | T9 | 2 | T29 | 9 | ||||
false | 13768 | 1 | T1 | 2 | T2 | 5 | T3 | 1 | ||||
true | 4100 | 1 | T2 | 1 | T4 | 11 | T9 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |