Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24549106	15163	0	0
intr_enable_rd_A	24549106	51116	0	0
reset_en_rd_A	24549106	1685	0	0
reset_en_regwen_rd_A	24549106	1425	0	0
wake_info_capture_dis_rd_A	24549106	1488	0	0
wakeup_en_rd_A	24549106	2454	0	0
wakeup_en_regwen_rd_A	24549106	1370	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	15163	0	0
T21	394195	68	0	0
T22	0	55	0	0
T23	0	32	0	0
T39	39216	0	0	0
T50	0	21	0	0
T51	0	9	0	0
T83	10081	0	0	0
T84	4326	0	0	0
T85	18792	0	0	0
T86	1770	0	0	0
T87	13842	0	0	0
T88	3377	0	0	0
T89	2192	0	0	0
T90	53121	0	0	0
T122	0	10	0	0
T123	0	18	0	0
T124	0	10	0	0
T125	0	2	0	0
T126	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	51116	0	0
T4	103398	208	0	0
T5	15135	0	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	0	0	0
T10	18353	0	0	0
T11	516	0	0	0
T13	1361	0	0	0
T14	0	5	0	0
T18	13029	0	0	0
T24	0	18	0	0
T25	0	10	0	0
T26	0	181	0	0
T31	0	20	0	0
T34	0	572	0	0
T35	0	22	0	0
T78	0	72	0	0
T127	0	14	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	1685	0	0
T23	495900	14	0	0
T44	4743	0	0	0
T51	0	1	0	0
T81	0	8	0	0
T94	30472	0	0	0
T95	1860	0	0	0
T123	0	10	0	0
T128	0	12	0	0
T129	0	1	0	0
T130	0	6	0	0
T131	0	7	0	0
T132	0	13	0	0
T133	0	7	0	0
T134	2043	0	0	0
T135	5038	0	0	0
T136	22692	0	0	0
T137	1605	0	0	0
T138	1023	0	0	0
T139	2922	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	1425	0	0
T23	495900	9	0	0
T44	4743	0	0	0
T51	0	2	0	0
T94	30472	0	0	0
T95	1860	0	0	0
T123	0	9	0	0
T128	0	16	0	0
T129	0	9	0	0
T130	0	2	0	0
T131	0	4	0	0
T132	0	9	0	0
T133	0	5	0	0
T134	2043	0	0	0
T135	5038	0	0	0
T136	22692	0	0	0
T137	1605	0	0	0
T138	1023	0	0	0
T139	2922	0	0	0
T140	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	1488	0	0
T23	495900	9	0	0
T44	4743	0	0	0
T51	0	8	0	0
T94	30472	0	0	0
T95	1860	0	0	0
T128	0	14	0	0
T130	0	10	0	0
T131	0	3	0	0
T132	0	6	0	0
T133	0	11	0	0
T134	2043	0	0	0
T135	5038	0	0	0
T136	22692	0	0	0
T137	1605	0	0	0
T138	1023	0	0	0
T139	2922	0	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	0	12	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	2454	0	0
T23	495900	6	0	0
T44	4743	0	0	0
T51	0	12	0	0
T81	0	9	0	0
T94	30472	0	0	0
T95	1860	0	0	0
T123	0	9	0	0
T128	0	14	0	0
T129	0	14	0	0
T130	0	2	0	0
T131	0	13	0	0
T132	0	7	0	0
T133	0	4	0	0
T134	2043	0	0	0
T135	5038	0	0	0
T136	22692	0	0	0
T137	1605	0	0	0
T138	1023	0	0	0
T139	2922	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24549106	1370	0	0
T23	495900	8	0	0
T44	4743	0	0	0
T51	0	2	0	0
T81	0	1	0	0
T94	30472	0	0	0
T95	1860	0	0	0
T123	0	4	0	0
T128	0	15	0	0
T129	0	12	0	0
T130	0	9	0	0
T131	0	2	0	0
T132	0	16	0	0
T133	0	5	0	0
T134	2043	0	0	0
T135	5038	0	0	0
T136	22692	0	0	0
T137	1605	0	0	0
T138	1023	0	0	0
T139	2922	0	0	0